llvm/test/CodeGen/AMDGPU/bfm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck --check-prefix=SI %s
; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck --check-prefix=VI %s

define amdgpu_kernel void @s_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
; SI-LABEL: s_bfm_pattern:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]
; SI-NEXT:    s_bfm_b32 s4, s4, s5
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: s_bfm_pattern:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_bfm_b32 s2, s2, s3
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    v_mov_b32_e32 v2, s2
; VI-NEXT:    flat_store_dword v[0:1], v2
; VI-NEXT:    s_endpgm
  %a = shl i32 1, %x
  %b = sub i32 %a, 1
  %c = shl i32 %b, %y
  store i32 %c, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @s_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {
; SI-LABEL: s_bfm_pattern_simple:
; SI:       ; %bb.0:
; SI-NEXT:    s_load_dword s6, s[4:5], 0xb
; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT:    s_mov_b32 s3, 0xf000
; SI-NEXT:    s_mov_b32 s2, -1
; SI-NEXT:    s_waitcnt lgkmcnt(0)
; SI-NEXT:    s_bfm_b32 s4, s6, 0
; SI-NEXT:    v_mov_b32_e32 v0, s4
; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT:    s_endpgm
;
; VI-LABEL: s_bfm_pattern_simple:
; VI:       ; %bb.0:
; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c
; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT:    s_waitcnt lgkmcnt(0)
; VI-NEXT:    s_bfm_b32 s2, s2, 0
; VI-NEXT:    v_mov_b32_e32 v0, s0
; VI-NEXT:    v_mov_b32_e32 v1, s1
; VI-NEXT:    v_mov_b32_e32 v2, s2
; VI-NEXT:    flat_store_dword v[0:1], v2
; VI-NEXT:    s_endpgm
  %a = shl i32 1, %x
  %b = sub i32 %a, 1
  store i32 %b, ptr addrspace(1) %out
  ret void
}

define void @v_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
; SI-LABEL: v_bfm_pattern:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_mov_b32 s6, 0
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s4, s6
; SI-NEXT:    s_mov_b32 s5, s6
; SI-NEXT:    v_bfm_b32_e32 v2, v2, v3
; SI-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: v_bfm_pattern:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_bfm_b32 v2, v2, v3
; VI-NEXT:    flat_store_dword v[0:1], v2
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %a = shl i32 1, %x
  %b = sub i32 %a, 1
  %c = shl i32 %b, %y
  store i32 %c, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps i64 @s_bfm64_pattern(i64 inreg %x, i64 inreg %y) {
; SI-LABEL: s_bfm64_pattern:
; SI:       ; %bb.0:
; SI-NEXT:    s_bfm_b64 s[0:1], s0, s2
; SI-NEXT:    ; return to shader part epilog
;
; VI-LABEL: s_bfm64_pattern:
; VI:       ; %bb.0:
; VI-NEXT:    s_bfm_b64 s[0:1], s0, s2
; VI-NEXT:    ; return to shader part epilog
  %a = shl i64 1, %x
  %b = sub i64 %a, 1
  %c = shl i64 %b, %y
  ret i64 %c
}

define amdgpu_ps i64 @s_bfm64_pattern_simple(i64 inreg %x) {
; SI-LABEL: s_bfm64_pattern_simple:
; SI:       ; %bb.0:
; SI-NEXT:    s_bfm_b64 s[0:1], s0, 0
; SI-NEXT:    ; return to shader part epilog
;
; VI-LABEL: s_bfm64_pattern_simple:
; VI:       ; %bb.0:
; VI-NEXT:    s_bfm_b64 s[0:1], s0, 0
; VI-NEXT:    ; return to shader part epilog
  %a = shl i64 1, %x
  %b = sub i64 %a, 1
  ret i64 %b
}

define void @v_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {
; SI-LABEL: v_bfm_pattern_simple:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    s_mov_b32 s6, 0
; SI-NEXT:    s_mov_b32 s7, 0xf000
; SI-NEXT:    s_mov_b32 s4, s6
; SI-NEXT:    s_mov_b32 s5, s6
; SI-NEXT:    v_bfm_b32_e64 v2, v2, 0
; SI-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: v_bfm_pattern_simple:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_bfm_b32 v2, v2, 0
; VI-NEXT:    flat_store_dword v[0:1], v2
; VI-NEXT:    s_waitcnt vmcnt(0)
; VI-NEXT:    s_setpc_b64 s[30:31]
  %a = shl i32 1, %x
  %b = sub i32 %a, 1
  store i32 %b, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps <2 x i64> @s_bfm64_v2i64_pattern(<2 x i64> inreg %x, <2 x i64> inreg %y) {
; SI-LABEL: s_bfm64_v2i64_pattern:
; SI:       ; %bb.0:
; SI-NEXT:    s_bfm_b64 s[2:3], s2, s6
; SI-NEXT:    s_bfm_b64 s[0:1], s0, s4
; SI-NEXT:    ; return to shader part epilog
;
; VI-LABEL: s_bfm64_v2i64_pattern:
; VI:       ; %bb.0:
; VI-NEXT:    s_bfm_b64 s[2:3], s2, s6
; VI-NEXT:    s_bfm_b64 s[0:1], s0, s4
; VI-NEXT:    ; return to shader part epilog
  %a = shl <2 x i64> splat (i64 1), %x
  %b = sub <2 x i64> %a, splat (i64 1)
  %c = shl <2 x i64> %b, %y
  ret <2 x i64> %c
}

define amdgpu_ps <2 x i64> @s_bfm64_v2i64_pattern_simple(<2 x i64> inreg %x) {
; SI-LABEL: s_bfm64_v2i64_pattern_simple:
; SI:       ; %bb.0:
; SI-NEXT:    s_bfm_b64 s[2:3], s2, 0
; SI-NEXT:    s_bfm_b64 s[0:1], s0, 0
; SI-NEXT:    ; return to shader part epilog
;
; VI-LABEL: s_bfm64_v2i64_pattern_simple:
; VI:       ; %bb.0:
; VI-NEXT:    s_bfm_b64 s[2:3], s2, 0
; VI-NEXT:    s_bfm_b64 s[0:1], s0, 0
; VI-NEXT:    ; return to shader part epilog
  %a = shl <2 x i64> splat (i64 1), %x
  %b = sub <2 x i64> %a, splat (i64 1)
  ret <2 x i64> %b
}

define i64 @v_bfm64_pattern(i64 %x, i64 %y) {
; SI-LABEL: v_bfm64_pattern:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshl_b64 v[0:1], 1, v0
; SI-NEXT:    v_add_i32_e32 v0, vcc, -1, v0
; SI-NEXT:    v_addc_u32_e32 v1, vcc, -1, v1, vcc
; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], v2
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: v_bfm64_pattern:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshlrev_b64 v[0:1], v0, 1
; VI-NEXT:    v_add_u32_e32 v0, vcc, -1, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, -1, v1, vcc
; VI-NEXT:    v_lshlrev_b64 v[0:1], v2, v[0:1]
; VI-NEXT:    s_setpc_b64 s[30:31]
  %a = shl i64 1, %x
  %b = sub i64 %a, 1
  %c = shl i64 %b, %y
  ret i64 %c
}

define i64 @v_bfm64_pattern_simple(i64 %x) {
; SI-LABEL: v_bfm64_pattern_simple:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshl_b64 v[0:1], 1, v0
; SI-NEXT:    v_add_i32_e32 v0, vcc, -1, v0
; SI-NEXT:    v_addc_u32_e32 v1, vcc, -1, v1, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: v_bfm64_pattern_simple:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshlrev_b64 v[0:1], v0, 1
; VI-NEXT:    v_add_u32_e32 v0, vcc, -1, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, -1, v1, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
  %a = shl i64 1, %x
  %b = sub i64 %a, 1
  ret i64 %b
}

define <2 x i64> @v_bfm64_v2i64_pattern(<2 x i64> %x, <2 x i64> %y) {
; SI-LABEL: v_bfm64_v2i64_pattern:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshl_b64 v[2:3], 1, v2
; SI-NEXT:    v_lshl_b64 v[0:1], 1, v0
; SI-NEXT:    v_add_i32_e32 v2, vcc, -1, v2
; SI-NEXT:    v_addc_u32_e32 v3, vcc, -1, v3, vcc
; SI-NEXT:    v_add_i32_e32 v0, vcc, -1, v0
; SI-NEXT:    v_addc_u32_e32 v1, vcc, -1, v1, vcc
; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], v4
; SI-NEXT:    v_lshl_b64 v[2:3], v[2:3], v6
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: v_bfm64_v2i64_pattern:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshlrev_b64 v[2:3], v2, 1
; VI-NEXT:    v_lshlrev_b64 v[0:1], v0, 1
; VI-NEXT:    v_add_u32_e32 v2, vcc, -1, v2
; VI-NEXT:    v_addc_u32_e32 v3, vcc, -1, v3, vcc
; VI-NEXT:    v_add_u32_e32 v0, vcc, -1, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, -1, v1, vcc
; VI-NEXT:    v_lshlrev_b64 v[0:1], v4, v[0:1]
; VI-NEXT:    v_lshlrev_b64 v[2:3], v6, v[2:3]
; VI-NEXT:    s_setpc_b64 s[30:31]
  %a = shl <2 x i64> splat (i64 1), %x
  %b = sub <2 x i64> %a, splat (i64 1)
  %c = shl <2 x i64> %b, %y
  ret <2 x i64> %c
}

define <2 x i64> @v_bfm64_v2i64_pattern_simple(<2 x i64> %x) {
; SI-LABEL: v_bfm64_v2i64_pattern_simple:
; SI:       ; %bb.0:
; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT:    v_lshl_b64 v[0:1], 1, v0
; SI-NEXT:    v_lshl_b64 v[2:3], 1, v2
; SI-NEXT:    v_add_i32_e32 v0, vcc, -1, v0
; SI-NEXT:    v_addc_u32_e32 v1, vcc, -1, v1, vcc
; SI-NEXT:    v_add_i32_e32 v2, vcc, -1, v2
; SI-NEXT:    v_addc_u32_e32 v3, vcc, -1, v3, vcc
; SI-NEXT:    s_setpc_b64 s[30:31]
;
; VI-LABEL: v_bfm64_v2i64_pattern_simple:
; VI:       ; %bb.0:
; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT:    v_lshlrev_b64 v[0:1], v0, 1
; VI-NEXT:    v_lshlrev_b64 v[2:3], v2, 1
; VI-NEXT:    v_add_u32_e32 v0, vcc, -1, v0
; VI-NEXT:    v_addc_u32_e32 v1, vcc, -1, v1, vcc
; VI-NEXT:    v_add_u32_e32 v2, vcc, -1, v2
; VI-NEXT:    v_addc_u32_e32 v3, vcc, -1, v3, vcc
; VI-NEXT:    s_setpc_b64 s[30:31]
  %a = shl <2 x i64> splat (i64 1), %x
  %b = sub <2 x i64> %a, splat (i64 1)
  ret <2 x i64> %b
}

attributes #0 = { nounwind }