llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 4
; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck -check-prefixes=CHECK,PRELINK %s
; RUN: opt -S -mtriple=amdgpu-amd-amdhsa -passes=amdgpu-simplifylib,instcombine %s | FileCheck -check-prefixes=CHECK,NOPRELINK %s

declare float @_Z5rootnfi(float, i32)
declare <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float>, <2 x i32>)
declare <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float>, <3 x i32>)
declare <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float>, <4 x i32>)
declare <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float>, <8 x i32>)
declare <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float>, <16 x i32>)
declare double @_Z5rootndi(double, i32)
declare <2 x double> @_Z5rootnDv2_dDv2_i(<2 x double>, <2 x i32>)
declare <3 x double> @_Z5rootnDv3_dDv3_i(<3 x double>, <3 x i32>)
declare <4 x double> @_Z5rootnDv4_dDv4_i(<4 x double>, <4 x i32>)
declare <8 x double> @_Z5rootnDv8_dDv8_i(<8 x double>, <8 x i32>)
declare <16 x double> @_Z5rootnDv16_dDv16_i(<16 x double>, <16 x i32>)
declare half @_Z5rootnDhi(half, i32)
declare <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half>, <2 x i32>)
declare <3 x half> @_Z5rootnDv3_DhDv3_i(<3 x half>, <3 x i32>)
declare <4 x half> @_Z5rootnDv4_DhDv4_i(<4 x half>, <4 x i32>)
declare <8 x half> @_Z5rootnDv8_DhDv8_i(<8 x half>, <8 x i32>)
declare <16 x half> @_Z5rootnDv16_DhDv16_i(<16 x half>, <16 x i32>)

define float @test_rootn_f32(float %x, i32 %y) {
; CHECK-LABEL: define float @test_rootn_f32(
; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 [[Y]])
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 %y)
  ret float %call
}

define float @test_rootn_f32_flags(float %x, i32 %y) {
; CHECK-LABEL: define float @test_rootn_f32_flags(
; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call nnan nsz float @_Z5rootnfi(float [[X]], i32 [[Y]])
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call nnan nsz float @_Z5rootnfi(float %x, i32 %y)
  ret float %call
}

define <2 x float> @test_rootn_v2f32(<2 x float> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32(
; CHECK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
  ret <2 x float> %call
}

define <3 x float> @test_rootn_v3f32(<3 x float> %x, <3 x i32> %y) {
; CHECK-LABEL: define <3 x float> @test_rootn_v3f32(
; CHECK-SAME: <3 x float> [[X:%.*]], <3 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> [[X]], <3 x i32> [[Y]])
; CHECK-NEXT:    ret <3 x float> [[CALL]]
;
entry:
  %call = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> %x, <3 x i32> %y)
  ret <3 x float> %call
}

define <4 x float> @test_rootn_v4f32(<4 x float> %x, <4 x i32> %y) {
; CHECK-LABEL: define <4 x float> @test_rootn_v4f32(
; CHECK-SAME: <4 x float> [[X:%.*]], <4 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float> [[X]], <4 x i32> [[Y]])
; CHECK-NEXT:    ret <4 x float> [[CALL]]
;
entry:
  %call = tail call <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float> %x, <4 x i32> %y)
  ret <4 x float> %call
}

define <8 x float> @test_rootn_v8f32(<8 x float> %x, <8 x i32> %y) {
; CHECK-LABEL: define <8 x float> @test_rootn_v8f32(
; CHECK-SAME: <8 x float> [[X:%.*]], <8 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float> [[X]], <8 x i32> [[Y]])
; CHECK-NEXT:    ret <8 x float> [[CALL]]
;
entry:
  %call = tail call <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float> %x, <8 x i32> %y)
  ret <8 x float> %call
}

define <16 x float> @test_rootn_v16f32(<16 x float> %x, <16 x i32> %y) {
; CHECK-LABEL: define <16 x float> @test_rootn_v16f32(
; CHECK-SAME: <16 x float> [[X:%.*]], <16 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float> [[X]], <16 x i32> [[Y]])
; CHECK-NEXT:    ret <16 x float> [[CALL]]
;
entry:
  %call = tail call <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float> %x, <16 x i32> %y)
  ret <16 x float> %call
}

define double @test_rootn_f64(double %x, i32 %y) {
; CHECK-LABEL: define double @test_rootn_f64(
; CHECK-SAME: double [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call double @_Z5rootndi(double [[X]], i32 [[Y]])
; CHECK-NEXT:    ret double [[CALL]]
;
entry:
  %call = tail call double @_Z5rootndi(double %x, i32 %y)
  ret double %call
}

define <2 x double> @test_rootn_v2f64(<2 x double> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x double> @test_rootn_v2f64(
; CHECK-SAME: <2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x double> @_Z5rootnDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x double> [[CALL]]
;
entry:
  %call = tail call <2 x double> @_Z5rootnDv2_dDv2_i(<2 x double> %x, <2 x i32> %y)
  ret <2 x double> %call
}

define <3 x double> @test_rootn_v3f64(<3 x double> %x, <3 x i32> %y) {
; CHECK-LABEL: define <3 x double> @test_rootn_v3f64(
; CHECK-SAME: <3 x double> [[X:%.*]], <3 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <3 x double> @_Z5rootnDv3_dDv3_i(<3 x double> [[X]], <3 x i32> [[Y]])
; CHECK-NEXT:    ret <3 x double> [[CALL]]
;
entry:
  %call = tail call <3 x double> @_Z5rootnDv3_dDv3_i(<3 x double> %x, <3 x i32> %y)
  ret <3 x double> %call
}

define <4 x double> @test_rootn_v4f64(<4 x double> %x, <4 x i32> %y) {
; CHECK-LABEL: define <4 x double> @test_rootn_v4f64(
; CHECK-SAME: <4 x double> [[X:%.*]], <4 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <4 x double> @_Z5rootnDv4_dDv4_i(<4 x double> [[X]], <4 x i32> [[Y]])
; CHECK-NEXT:    ret <4 x double> [[CALL]]
;
entry:
  %call = tail call <4 x double> @_Z5rootnDv4_dDv4_i(<4 x double> %x, <4 x i32> %y)
  ret <4 x double> %call
}

define <8 x double> @test_rootn_v8f64(<8 x double> %x, <8 x i32> %y) {
; CHECK-LABEL: define <8 x double> @test_rootn_v8f64(
; CHECK-SAME: <8 x double> [[X:%.*]], <8 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <8 x double> @_Z5rootnDv8_dDv8_i(<8 x double> [[X]], <8 x i32> [[Y]])
; CHECK-NEXT:    ret <8 x double> [[CALL]]
;
entry:
  %call = tail call <8 x double> @_Z5rootnDv8_dDv8_i(<8 x double> %x, <8 x i32> %y)
  ret <8 x double> %call
}

define <16 x double> @test_rootn_v16f64(<16 x double> %x, <16 x i32> %y) {
; CHECK-LABEL: define <16 x double> @test_rootn_v16f64(
; CHECK-SAME: <16 x double> [[X:%.*]], <16 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <16 x double> @_Z5rootnDv16_dDv16_i(<16 x double> [[X]], <16 x i32> [[Y]])
; CHECK-NEXT:    ret <16 x double> [[CALL]]
;
entry:
  %call = tail call <16 x double> @_Z5rootnDv16_dDv16_i(<16 x double> %x, <16 x i32> %y)
  ret <16 x double> %call
}

define half @test_rootn_f16(half %x, i32 %y) {
; CHECK-LABEL: define half @test_rootn_f16(
; CHECK-SAME: half [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call half @_Z5rootnDhi(half [[X]], i32 [[Y]])
; CHECK-NEXT:    ret half [[CALL]]
;
entry:
  %call = tail call half @_Z5rootnDhi(half %x, i32 %y)
  ret half %call
}

define <2 x half> @test_rootn_v2f16(<2 x half> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16(
; CHECK-SAME: <2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x half> [[CALL]]
;
entry:
  %call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y)
  ret <2 x half> %call
}

define <3 x half> @test_rootn_v3f16(<3 x half> %x, <3 x i32> %y) {
; CHECK-LABEL: define <3 x half> @test_rootn_v3f16(
; CHECK-SAME: <3 x half> [[X:%.*]], <3 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <3 x half> @_Z5rootnDv3_DhDv3_i(<3 x half> [[X]], <3 x i32> [[Y]])
; CHECK-NEXT:    ret <3 x half> [[CALL]]
;
entry:
  %call = tail call <3 x half> @_Z5rootnDv3_DhDv3_i(<3 x half> %x, <3 x i32> %y)
  ret <3 x half> %call
}

define <4 x half> @test_rootn_v4f16(<4 x half> %x, <4 x i32> %y) {
; CHECK-LABEL: define <4 x half> @test_rootn_v4f16(
; CHECK-SAME: <4 x half> [[X:%.*]], <4 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <4 x half> @_Z5rootnDv4_DhDv4_i(<4 x half> [[X]], <4 x i32> [[Y]])
; CHECK-NEXT:    ret <4 x half> [[CALL]]
;
entry:
  %call = tail call <4 x half> @_Z5rootnDv4_DhDv4_i(<4 x half> %x, <4 x i32> %y)
  ret <4 x half> %call
}

define <8 x half> @test_rootn_v8f16(<8 x half> %x, <8 x i32> %y) {
; CHECK-LABEL: define <8 x half> @test_rootn_v8f16(
; CHECK-SAME: <8 x half> [[X:%.*]], <8 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <8 x half> @_Z5rootnDv8_DhDv8_i(<8 x half> [[X]], <8 x i32> [[Y]])
; CHECK-NEXT:    ret <8 x half> [[CALL]]
;
entry:
  %call = tail call <8 x half> @_Z5rootnDv8_DhDv8_i(<8 x half> %x, <8 x i32> %y)
  ret <8 x half> %call
}

define <16 x half> @test_rootn_v16f16(<16 x half> %x, <16 x i32> %y) {
; CHECK-LABEL: define <16 x half> @test_rootn_v16f16(
; CHECK-SAME: <16 x half> [[X:%.*]], <16 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <16 x half> @_Z5rootnDv16_DhDv16_i(<16 x half> [[X]], <16 x i32> [[Y]])
; CHECK-NEXT:    ret <16 x half> [[CALL]]
;
entry:
  %call = tail call <16 x half> @_Z5rootnDv16_DhDv16_i(<16 x half> %x, <16 x i32> %y)
  ret <16 x half> %call
}

define half @test_rootn_f16_0(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_0(
; CHECK-SAME: half [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call half @_Z5rootnDhi(half [[X]], i32 0)
; CHECK-NEXT:    ret half [[CALL]]
;
  %call = tail call half @_Z5rootnDhi(half %x, i32 0)
  ret half %call
}

define half @test_rootn_f16_1(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_1(
; CHECK-SAME: half [[X:%.*]]) {
; CHECK-NEXT:    ret half [[X]]
;
  %call = tail call half @_Z5rootnDhi(half %x, i32 1)
  ret half %call
}

define half @test_rootn_f16_2(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_2(
; CHECK-SAME: half [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call half @_Z5rootnDhi(half [[X]], i32 2)
; CHECK-NEXT:    ret half [[CALL]]
;
  %call = tail call half @_Z5rootnDhi(half %x, i32 2)
  ret half %call
}

define half @test_rootn_f16_3(half %x) {
; PRELINK-LABEL: define half @test_rootn_f16_3(
; PRELINK-SAME: half [[X:%.*]]) {
; PRELINK-NEXT:    [[__ROOTN2CBRT:%.*]] = call half @_Z4cbrtDh(half [[X]])
; PRELINK-NEXT:    ret half [[__ROOTN2CBRT]]
;
; NOPRELINK-LABEL: define half @test_rootn_f16_3(
; NOPRELINK-SAME: half [[X:%.*]]) {
; NOPRELINK-NEXT:    [[CALL:%.*]] = tail call half @_Z5rootnDhi(half [[X]], i32 3)
; NOPRELINK-NEXT:    ret half [[CALL]]
;
  %call = tail call half @_Z5rootnDhi(half %x, i32 3)
  ret half %call
}

define half @test_rootn_f16_neg1(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_neg1(
; CHECK-SAME: half [[X:%.*]]) {
; CHECK-NEXT:    [[__ROOTN2DIV:%.*]] = fdiv half 1.000000e+00, [[X]]
; CHECK-NEXT:    ret half [[__ROOTN2DIV]]
;
  %call = tail call half @_Z5rootnDhi(half %x, i32 -1)
  ret half %call
}

define half @test_rootn_f16_neg2(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_neg2(
; CHECK-SAME: half [[X:%.*]]) {
; CHECK-NEXT:    [[__ROOTN2RSQRT:%.*]] = tail call half @_Z5rootnDhi(half [[X]], i32 -2)
; CHECK-NEXT:    ret half [[__ROOTN2RSQRT]]
;
  %call = tail call half @_Z5rootnDhi(half %x, i32 -2)
  ret half %call
}

define half @test_rootn_f16_neg3(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_neg3(
; CHECK-SAME: half [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call half @_Z5rootnDhi(half [[X]], i32 -3)
; CHECK-NEXT:    ret half [[CALL]]
;
  %call = tail call half @_Z5rootnDhi(half %x, i32 -3)
  ret half %call
}

define half @test_rootn_f16_neg4(half %x) {
; CHECK-LABEL: define half @test_rootn_f16_neg4(
; CHECK-SAME: half [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call half @_Z5rootnDhi(half [[X]], i32 -4)
; CHECK-NEXT:    ret half [[CALL]]
;
  %call = tail call half @_Z5rootnDhi(half %x, i32 -4)
  ret half %call
}

define <2 x half> @test_rootn_v2f16_0(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16_0(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> zeroinitializer)
; CHECK-NEXT:    ret <2 x half> [[CALL]]
;
  %call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> zeroinitializer)
  ret <2 x half> %call
}

define <2 x half> @test_rootn_v2f16_1(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16_1(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
; CHECK-NEXT:    ret <2 x half> [[X]]
;
  %call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> <i32 1, i32 1>)
  ret <2 x half> %call
}

define <2 x half> @test_rootn_v2f16_2(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16_2(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> splat (i32 2))
; CHECK-NEXT:    ret <2 x half> [[CALL]]
;
  %call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> <i32 2, i32 2>)
  ret <2 x half> %call
}

define <2 x half> @test_rootn_v2f16_neg1(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16_neg1(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
; CHECK-NEXT:    [[__ROOTN2DIV:%.*]] = fdiv <2 x half> splat (half 1.000000e+00), [[X]]
; CHECK-NEXT:    ret <2 x half> [[__ROOTN2DIV]]
;
  %call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> <i32 -1, i32 -1>)
  ret <2 x half> %call
}

define <2 x half> @test_rootn_v2f16_neg2(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16_neg2(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
; CHECK-NEXT:    [[__ROOTN2RSQRT:%.*]] = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> splat (i32 -2))
; CHECK-NEXT:    ret <2 x half> [[__ROOTN2RSQRT]]
;
  %call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> <i32 -2, i32 -2>)
  ret <2 x half> %call
}

define <2 x half> @test_rootn_v2f16_neg3(<2 x half> %x) {
; CHECK-LABEL: define <2 x half> @test_rootn_v2f16_neg3(
; CHECK-SAME: <2 x half> [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> splat (i32 -3))
; CHECK-NEXT:    ret <2 x half> [[CALL]]
;
  %call = tail call <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> <i32 -3, i32 -3>)
  ret <2 x half> %call
}

define float @test_rootn_f32__y_0(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_0(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 0)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 0)
  ret float %call
}

define float @test_rootn_f32__y_poison(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_poison(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 poison)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 poison)
  ret float %call
}

define <2 x float> @test_rootn_v2f32__y_poison(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_poison(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> poison)
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> poison)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_v2f32__y_0(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_0(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> zeroinitializer)
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> zeroinitializer)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_v2f32__y_0_undef(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_0_undef(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 0, i32 poison>)
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 0, i32 poison>)
  ret <2 x float> %call
}

define <3 x float> @test_rootn_v3f32__y_0(<3 x float> %x) {
; CHECK-LABEL: define <3 x float> @test_rootn_v3f32__y_0(
; CHECK-SAME: <3 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> [[X]], <3 x i32> zeroinitializer)
; CHECK-NEXT:    ret <3 x float> [[CALL]]
;
entry:
  %call = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> %x, <3 x i32> zeroinitializer)
  ret <3 x float> %call
}

define <4 x float> @test_rootn_v4f32__y_0(<4 x float> %x) {
; CHECK-LABEL: define <4 x float> @test_rootn_v4f32__y_0(
; CHECK-SAME: <4 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float> [[X]], <4 x i32> zeroinitializer)
; CHECK-NEXT:    ret <4 x float> [[CALL]]
;
entry:
  %call = tail call <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float> %x, <4 x i32> zeroinitializer)
  ret <4 x float> %call
}

define <8 x float> @test_rootn_v8f32__y_0(<8 x float> %x) {
; CHECK-LABEL: define <8 x float> @test_rootn_v8f32__y_0(
; CHECK-SAME: <8 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float> [[X]], <8 x i32> zeroinitializer)
; CHECK-NEXT:    ret <8 x float> [[CALL]]
;
entry:
  %call = tail call <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float> %x, <8 x i32> zeroinitializer)
  ret <8 x float> %call
}

define <16 x float> @test_rootn_v16f32__y_0(<16 x float> %x) {
; CHECK-LABEL: define <16 x float> @test_rootn_v16f32__y_0(
; CHECK-SAME: <16 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float> [[X]], <16 x i32> zeroinitializer)
; CHECK-NEXT:    ret <16 x float> [[CALL]]
;
entry:
  %call = tail call <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float> %x, <16 x i32> zeroinitializer)
  ret <16 x float> %call
}

define float @test_rootn_f32__y_1(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_1(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    ret float [[X]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 1)
  ret float %call
}

define float @test_rootn_f32__y_1__strictfp(float %x) #1 {
; CHECK-LABEL: define float @test_rootn_f32__y_1__strictfp(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 1) #[[ATTR0]]
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 1) #1
  ret float %call
}

define <2 x float> @test_rootn_v2f32__y_1(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_1(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    ret <2 x float> [[X]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 1, i32 1>)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_v2f32__y_1__strictfp(<2 x float> %x) #1 {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_1__strictfp(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 1)) #[[ATTR0]]
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 1, i32 1>) #1
  ret <2 x float> %call
}

define <2 x float> @test_rootn_v2f32__y_1_undef(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_1_undef(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    ret <2 x float> [[X]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 1, i32 poison>)
  ret <2 x float> %call
}

define <3 x float> @test_rootn_v3f32__y_1(<3 x float> %x) {
; CHECK-LABEL: define <3 x float> @test_rootn_v3f32__y_1(
; CHECK-SAME: <3 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    ret <3 x float> [[X]]
;
entry:
  %call = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 1, i32 1, i32 1>)
  ret <3 x float> %call
}

define <3 x float> @test_rootn_v3f32__y_1_undef(<3 x float> %x) {
; CHECK-LABEL: define <3 x float> @test_rootn_v3f32__y_1_undef(
; CHECK-SAME: <3 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    ret <3 x float> [[X]]
;
entry:
  %call = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 1, i32 1, i32 poison>)
  ret <3 x float> %call
}

define <4 x float> @test_rootn_v4f32__y_1(<4 x float> %x) {
; CHECK-LABEL: define <4 x float> @test_rootn_v4f32__y_1(
; CHECK-SAME: <4 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    ret <4 x float> [[X]]
;
entry:
  %call = tail call <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float> %x, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
  ret <4 x float> %call
}

define <8 x float> @test_rootn_v8f32__y_1(<8 x float> %x) {
; CHECK-LABEL: define <8 x float> @test_rootn_v8f32__y_1(
; CHECK-SAME: <8 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    ret <8 x float> [[X]]
;
entry:
  %call = tail call <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float> %x, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>)
  ret <8 x float> %call
}

define <16 x float> @test_rootn_v16f32__y_1(<16 x float> %x) {
; CHECK-LABEL: define <16 x float> @test_rootn_v16f32__y_1(
; CHECK-SAME: <16 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    ret <16 x float> [[X]]
;
entry:
  %call = tail call <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float> %x, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>)
  ret <16 x float> %call
}

define float @test_rootn_f32__y_2(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_2(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 2)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 2)
  ret float %call
}

define float @test_rootn_f32__y_2_flags(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_2_flags(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call nnan nsz float @_Z5rootnfi(float [[X]], i32 2)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call nnan nsz float @_Z5rootnfi(float %x, i32 2)
  ret float %call
}

; nsz+ninf are required to legalize the rootn(-0.0,2)/rootn(-Inf,2) corners,
; so the fold should fire here.
define float @test_rootn_f32__y_2_nsz_ninf(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_2_nsz_ninf(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = call ninf nsz float @llvm.sqrt.f32(float [[X]]), !fpmath [[META1:![0-9]+]]
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call nsz ninf float @_Z5rootnfi(float %x, i32 2)
  ret float %call
}

; Should retain looser existing !fpmath requirements.
define float @test_rootn_f32__y_2_fpmath_3(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_2_fpmath_3(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call nnan nsz float @_Z5rootnfi(float [[X]], i32 2), !fpmath [[META2:![0-9]+]]
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call nnan nsz float @_Z5rootnfi(float %x, i32 2), !fpmath !0
  ret float %call
}

define <2 x float> @test_rootn_v2f32__y_2_flags(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_2_flags(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call nnan nsz <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 2))
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call nnan nsz <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 2, i32 2>)
  ret <2 x float> %call
}

define <3 x float> @test_rootn_v3f32__y_2(<3 x float> %x) {
; CHECK-LABEL: define <3 x float> @test_rootn_v3f32__y_2(
; CHECK-SAME: <3 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> [[X]], <3 x i32> splat (i32 2))
; CHECK-NEXT:    ret <3 x float> [[CALL]]
;
entry:
  %call = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 2, i32 2, i32 2>)
  ret <3 x float> %call
}

define <3 x float> @test_rootn_v3f32__y_2_undef(<3 x float> %x) {
; CHECK-LABEL: define <3 x float> @test_rootn_v3f32__y_2_undef(
; CHECK-SAME: <3 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> [[X]], <3 x i32> <i32 2, i32 poison, i32 2>)
; CHECK-NEXT:    ret <3 x float> [[CALL]]
;
entry:
  %call = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 2, i32 poison, i32 2>)
  ret <3 x float> %call
}

define <4 x float> @test_rootn_v4f32__y_2(<4 x float> %x) {
; CHECK-LABEL: define <4 x float> @test_rootn_v4f32__y_2(
; CHECK-SAME: <4 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float> [[X]], <4 x i32> splat (i32 2))
; CHECK-NEXT:    ret <4 x float> [[CALL]]
;
entry:
  %call = tail call <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float> %x, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)
  ret <4 x float> %call
}

define <8 x float> @test_rootn_v8f32__y_2(<8 x float> %x) {
; CHECK-LABEL: define <8 x float> @test_rootn_v8f32__y_2(
; CHECK-SAME: <8 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float> [[X]], <8 x i32> splat (i32 2))
; CHECK-NEXT:    ret <8 x float> [[CALL]]
;
entry:
  %call = tail call <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float> %x, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>)
  ret <8 x float> %call
}

define <16 x float> @test_rootn_v16f32__y_2(<16 x float> %x) {
; CHECK-LABEL: define <16 x float> @test_rootn_v16f32__y_2(
; CHECK-SAME: <16 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float> [[X]], <16 x i32> splat (i32 2))
; CHECK-NEXT:    ret <16 x float> [[CALL]]
;
entry:
  %call = tail call <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float> %x, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>)
  ret <16 x float> %call
}

define float @test_rootn_f32__y_3(float %x) {
; PRELINK-LABEL: define float @test_rootn_f32__y_3(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[__ROOTN2CBRT:%.*]] = call float @_Z4cbrtf(float [[X]])
; PRELINK-NEXT:    ret float [[__ROOTN2CBRT]]
;
; NOPRELINK-LABEL: define float @test_rootn_f32__y_3(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 3)
; NOPRELINK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 3)
  ret float %call
}

define <2 x float> @test_rootn_v2f32__y_3(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_rootn_v2f32__y_3(
; PRELINK-SAME: <2 x float> [[X:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[__ROOTN2CBRT:%.*]] = call <2 x float> @_Z4cbrtDv2_f(<2 x float> [[X]])
; PRELINK-NEXT:    ret <2 x float> [[__ROOTN2CBRT]]
;
; NOPRELINK-LABEL: define <2 x float> @test_rootn_v2f32__y_3(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[CALL:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 3))
; NOPRELINK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 3, i32 3>)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_v2f32__y_nonsplat_2_3(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_nonsplat_2_3(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 2, i32 3>)
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 2, i32 3>)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_v2f32__y_nonsplat_2_poison(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_nonsplat_2_poison(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 2, i32 poison>)
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 2, i32 poison>)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_v2f32__y_nonsplat_2_5(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_nonsplat_2_5(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 2, i32 5>)
; CHECK-NEXT:    ret <2 x float> [[CALL]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 2, i32 5>)
  ret <2 x float> %call
}

define float @test_rootn_f32__y_neg1(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg1(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2DIV:%.*]] = fdiv float 1.000000e+00, [[X]]
; CHECK-NEXT:    ret float [[__ROOTN2DIV]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 -1)
  ret float %call
}

define <2 x float> @test_rootn_v2f32__y_neg1(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_neg1(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2DIV:%.*]] = fdiv <2 x float> splat (float 1.000000e+00), [[X]]
; CHECK-NEXT:    ret <2 x float> [[__ROOTN2DIV]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -1, i32 -1>)
  ret <2 x float> %call
}

define <3 x float> @test_rootn_v3f32__y_neg1(<3 x float> %x) {
; CHECK-LABEL: define <3 x float> @test_rootn_v3f32__y_neg1(
; CHECK-SAME: <3 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2DIV:%.*]] = fdiv <3 x float> splat (float 1.000000e+00), [[X]]
; CHECK-NEXT:    ret <3 x float> [[__ROOTN2DIV]]
;
entry:
  %call = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 -1, i32 -1, i32 -1>)
  ret <3 x float> %call
}

define <3 x float> @test_rootn_v3f32__y_neg1_undef(<3 x float> %x) {
; CHECK-LABEL: define <3 x float> @test_rootn_v3f32__y_neg1_undef(
; CHECK-SAME: <3 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2DIV:%.*]] = fdiv <3 x float> splat (float 1.000000e+00), [[X]]
; CHECK-NEXT:    ret <3 x float> [[__ROOTN2DIV]]
;
entry:
  %call = tail call <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> %x, <3 x i32> <i32 -1, i32 -1, i32 poison>)
  ret <3 x float> %call
}

define <4 x float> @test_rootn_v4f32__y_neg1(<4 x float> %x) {
; CHECK-LABEL: define <4 x float> @test_rootn_v4f32__y_neg1(
; CHECK-SAME: <4 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2DIV:%.*]] = fdiv <4 x float> splat (float 1.000000e+00), [[X]]
; CHECK-NEXT:    ret <4 x float> [[__ROOTN2DIV]]
;
entry:
  %call = tail call <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float> %x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
  ret <4 x float> %call
}

define <8 x float> @test_rootn_v8f32__y_neg1(<8 x float> %x) {
; CHECK-LABEL: define <8 x float> @test_rootn_v8f32__y_neg1(
; CHECK-SAME: <8 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2DIV:%.*]] = fdiv <8 x float> splat (float 1.000000e+00), [[X]]
; CHECK-NEXT:    ret <8 x float> [[__ROOTN2DIV]]
;
entry:
  %call = tail call <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float> %x, <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>)
  ret <8 x float> %call
}

define <16 x float> @test_rootn_v16f32__y_neg1(<16 x float> %x) {
; CHECK-LABEL: define <16 x float> @test_rootn_v16f32__y_neg1(
; CHECK-SAME: <16 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2DIV:%.*]] = fdiv <16 x float> splat (float 1.000000e+00), [[X]]
; CHECK-NEXT:    ret <16 x float> [[__ROOTN2DIV]]
;
entry:
  %call = tail call <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float> %x, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>)
  ret <16 x float> %call
}

define float @test_rootn_f32__y_neg2(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg2(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2RSQRT:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2)
; CHECK-NEXT:    ret float [[__ROOTN2RSQRT]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 -2)
  ret float %call
}

define float @test_rootn_f32__y_neg2__flags(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg2__flags(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2RSQRT:%.*]] = tail call nnan nsz float @_Z5rootnfi(float [[X]], i32 -2)
; CHECK-NEXT:    ret float [[__ROOTN2RSQRT]]
;
entry:
  %call = tail call nsz nnan float @_Z5rootnfi(float %x, i32 -2)
  ret float %call
}

; nsz+ninf are required to legalize the rootn(-0.0,-2)/rootn(-Inf,-2)
; corners, so the rsqrt fold should fire here.
define float @test_rootn_f32__y_neg2__nsz_ninf(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg2__nsz_ninf(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP0:%.*]] = call ninf nsz contract float @llvm.sqrt.f32(float [[X]])
; CHECK-NEXT:    [[TMP1:%.*]] = fdiv ninf nsz contract float 1.000000e+00, [[TMP0]], !fpmath [[META1]]
; CHECK-NEXT:    ret float [[TMP1]]
;
entry:
  %call = tail call nsz ninf float @_Z5rootnfi(float %x, i32 -2)
  ret float %call
}

define float @test_rootn_f32__y_neg2__strictfp(float %x) #1 {
; CHECK-LABEL: define float @test_rootn_f32__y_neg2__strictfp(
; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2RSQRT:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2) #[[ATTR0]]
; CHECK-NEXT:    ret float [[__ROOTN2RSQRT]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 -2) #1
  ret float %call
}

define float @test_rootn_f32__y_neg2__noinline(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg2__noinline(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2) #[[ATTR3:[0-9]+]]
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 -2) #2
  ret float %call
}

define float @test_rootn_f32__y_neg2__nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg2__nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2) #[[ATTR4:[0-9]+]]
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 -2) #0
  ret float %call
}

define <2 x float> @test_rootn_v2f32__y_neg2(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_neg2(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2RSQRT:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -2))
; CHECK-NEXT:    ret <2 x float> [[__ROOTN2RSQRT]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -2, i32 -2>)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_v2f32__y_neg2__flags(<2 x float> %x) {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_neg2__flags(
; CHECK-SAME: <2 x float> [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2RSQRT:%.*]] = tail call nnan nsz <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -2))
; CHECK-NEXT:    ret <2 x float> [[__ROOTN2RSQRT]]
;
entry:
  %call = tail call nsz nnan <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -2, i32 -2>)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_v2f32__y_neg2__strictfp(<2 x float> %x) #1 {
; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_neg2__strictfp(
; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[__ROOTN2RSQRT:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -2)) #[[ATTR0]]
; CHECK-NEXT:    ret <2 x float> [[__ROOTN2RSQRT]]
;
entry:
  %call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -2, i32 -2>) #1
  ret <2 x float> %call
}

define float @test_rootn_f32__y_neg3(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg3(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -3)
; CHECK-NEXT:    ret float [[CALL]]
;
  %call = tail call float @_Z5rootnfi(float %x, i32 -3)
  ret float %call
}

define float @test_rootn_f32__y_neg4(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg4(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -4)
; CHECK-NEXT:    ret float [[CALL]]
;
  %call = tail call float @_Z5rootnfi(float %x, i32 -4)
  ret float %call
}

define float @test_rootn_afn_f32(float %x, i32 %y) {
; PRELINK-LABEL: define float @test_rootn_afn_f32(
; PRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call afn float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_f32(
; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP0:%.*]] = sitofp afn i32 [[Y]] to float
; NOPRELINK-NEXT:    [[TMP1:%.*]] = fdiv nnan afn float 1.000000e+00, [[TMP0]]
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = call afn float @llvm.log2.f32(float [[TMP2]])
; NOPRELINK-NEXT:    [[TMP4:%.*]] = fmul afn float [[TMP1]], [[TMP3]]
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call afn float @llvm.exp2.f32(float [[TMP4]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = and i32 [[Y]], 1
; NOPRELINK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], +inf
; NOPRELINK-NEXT:    [[TMP11:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
; NOPRELINK-NEXT:    [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
; NOPRELINK-NEXT:    [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
; NOPRELINK-NEXT:    [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
; NOPRELINK-NEXT:    [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
; NOPRELINK-NEXT:    [[TMP19:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP20:%.*]] = and i1 [[TMP19]], [[DOTNOT]]
; NOPRELINK-NEXT:    [[TMP21:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP22:%.*]] = or i1 [[TMP20]], [[TMP21]]
; NOPRELINK-NEXT:    [[TMP23:%.*]] = select afn i1 [[TMP22]], float +qnan, float [[TMP18]]
; NOPRELINK-NEXT:    ret float [[TMP23]]
;
entry:
  %call = tail call afn float @_Z5rootnfi(float %x, i32 %y)
  ret float %call
}

define <2 x float> @test_rootn_afn_v2f32(<2 x float> %x, <2 x i32> %y) {
; PRELINK-LABEL: define <2 x float> @test_rootn_afn_v2f32(
; PRELINK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
; PRELINK-NEXT:    ret <2 x float> [[CALL]]
;
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_v2f32(
; NOPRELINK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP0:%.*]] = sitofp afn <2 x i32> [[Y]] to <2 x float>
; NOPRELINK-NEXT:    [[TMP1:%.*]] = fdiv nnan afn <2 x float> splat (float 1.000000e+00), [[TMP0]]
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT:    [[TMP4:%.*]] = fmul afn <2 x float> [[TMP1]], [[TMP3]]
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP4]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = and <2 x i32> [[Y]], splat (i32 1)
; NOPRELINK-NEXT:    [[DOTNOT:%.*]] = icmp eq <2 x i32> [[TMP6]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP5]], <2 x float> [[TMP7]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], splat (float +inf)
; NOPRELINK-NEXT:    [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP12:%.*]] = or <2 x i1> [[TMP10]], [[TMP11]]
; NOPRELINK-NEXT:    [[TMP13:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP14:%.*]] = xor <2 x i1> [[TMP11]], [[TMP13]]
; NOPRELINK-NEXT:    [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT:    [[TMP16:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[X]]
; NOPRELINK-NEXT:    [[TMP17:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP15]], <2 x float> [[TMP16]])
; NOPRELINK-NEXT:    [[TMP18:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[TMP17]], <2 x float> [[TMP8]]
; NOPRELINK-NEXT:    [[TMP19:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[DOTNOT]]
; NOPRELINK-NEXT:    [[TMP21:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP22:%.*]] = or <2 x i1> [[TMP20]], [[TMP21]]
; NOPRELINK-NEXT:    [[TMP23:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> splat (float +qnan), <2 x float> [[TMP18]]
; NOPRELINK-NEXT:    ret <2 x float> [[TMP23]]
;
entry:
  %call = tail call afn <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
  ret <2 x float> %call
}

define double @test_rootn_afn_f64(double %x, i32 %y) {
; CHECK-LABEL: define double @test_rootn_afn_f64(
; CHECK-SAME: double [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn double @_Z5rootndi(double [[X]], i32 [[Y]])
; CHECK-NEXT:    ret double [[CALL]]
;
entry:
  %call = tail call afn double @_Z5rootndi(double %x, i32 %y)
  ret double %call
}

define <2 x double> @test_rootn_afn_v2f64(<2 x double> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x double> @test_rootn_afn_v2f64(
; CHECK-SAME: <2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <2 x double> @_Z5rootnDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x double> [[CALL]]
;
entry:
  %call = tail call afn <2 x double> @_Z5rootnDv2_dDv2_i(<2 x double> %x, <2 x i32> %y)
  ret <2 x double> %call
}

define half @test_rootn_afn_f16(half %x, i32 %y) {
; CHECK-LABEL: define half @test_rootn_afn_f16(
; CHECK-SAME: half [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn half @_Z5rootnDhi(half [[X]], i32 [[Y]])
; CHECK-NEXT:    ret half [[CALL]]
;
entry:
  %call = tail call afn half @_Z5rootnDhi(half %x, i32 %y)
  ret half %call
}

define <2 x half> @test_rootn_afn_v2f16(<2 x half> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x half> @test_rootn_afn_v2f16(
; CHECK-SAME: <2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call afn <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x half> [[CALL]]
;
entry:
  %call = tail call afn <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y)
  ret <2 x half> %call
}

define float @test_rootn_afn_nnan_ninf_f32(float %x, i32 %y) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32(
; PRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32(
; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP0:%.*]] = sitofp nnan ninf afn i32 [[Y]] to float
; NOPRELINK-NEXT:    [[TMP1:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[TMP0]]
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP2]])
; NOPRELINK-NEXT:    [[TMP4:%.*]] = fmul nnan ninf afn float [[TMP1]], [[TMP3]]
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP4]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = and i32 [[Y]], 1
; NOPRELINK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP10:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP11:%.*]] = xor i1 [[TMP9]], [[TMP10]]
; NOPRELINK-NEXT:    [[TMP12:%.*]] = select nnan ninf afn i1 [[TMP11]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP13:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
; NOPRELINK-NEXT:    [[TMP14:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP12]], float [[TMP13]])
; NOPRELINK-NEXT:    [[TMP15:%.*]] = select nnan ninf afn i1 [[TMP9]], float [[TMP14]], float [[TMP8]]
; NOPRELINK-NEXT:    [[TMP16:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP17:%.*]] = and i1 [[TMP16]], [[DOTNOT]]
; NOPRELINK-NEXT:    [[TMP18:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP19:%.*]] = or i1 [[TMP17]], [[TMP18]]
; NOPRELINK-NEXT:    [[TMP20:%.*]] = select nnan ninf afn i1 [[TMP19]], float +qnan, float [[TMP15]]
; NOPRELINK-NEXT:    ret float [[TMP20]]
;
entry:
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 %y)
  ret float %call
}

define <2 x float> @test_rootn_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y) {
; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32(
; PRELINK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
; PRELINK-NEXT:    ret <2 x float> [[CALL]]
;
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32(
; NOPRELINK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP0:%.*]] = sitofp nnan ninf afn <2 x i32> [[Y]] to <2 x float>
; NOPRELINK-NEXT:    [[TMP1:%.*]] = fdiv nnan ninf afn <2 x float> splat (float 1.000000e+00), [[TMP0]]
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP2]])
; NOPRELINK-NEXT:    [[TMP4:%.*]] = fmul nnan ninf afn <2 x float> [[TMP1]], [[TMP3]]
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP4]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = and <2 x i32> [[Y]], splat (i32 1)
; NOPRELINK-NEXT:    [[DOTNOT:%.*]] = icmp eq <2 x i32> [[TMP6]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP5]], <2 x float> [[TMP7]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP10:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP11:%.*]] = xor <2 x i1> [[TMP9]], [[TMP10]]
; NOPRELINK-NEXT:    [[TMP12:%.*]] = select nnan ninf afn <2 x i1> [[TMP11]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT:    [[TMP13:%.*]] = select nnan ninf afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[X]]
; NOPRELINK-NEXT:    [[TMP14:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP12]], <2 x float> [[TMP13]])
; NOPRELINK-NEXT:    [[TMP15:%.*]] = select nnan ninf afn <2 x i1> [[TMP9]], <2 x float> [[TMP14]], <2 x float> [[TMP8]]
; NOPRELINK-NEXT:    [[TMP16:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP17:%.*]] = and <2 x i1> [[TMP16]], [[DOTNOT]]
; NOPRELINK-NEXT:    [[TMP18:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP19:%.*]] = or <2 x i1> [[TMP17]], [[TMP18]]
; NOPRELINK-NEXT:    [[TMP20:%.*]] = select nnan ninf afn <2 x i1> [[TMP19]], <2 x float> splat (float +qnan), <2 x float> [[TMP15]]
; NOPRELINK-NEXT:    ret <2 x float> [[TMP20]]
;
entry:
  %call = tail call nnan ninf afn <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
  ret <2 x float> %call
}

define double @test_rootn_afn_nnan_ninf_f64(double %x, i32 %y) {
; CHECK-LABEL: define double @test_rootn_afn_nnan_ninf_f64(
; CHECK-SAME: double [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn double @_Z5rootndi(double [[X]], i32 [[Y]])
; CHECK-NEXT:    ret double [[CALL]]
;
entry:
  %call = tail call nnan ninf afn double @_Z5rootndi(double %x, i32 %y)
  ret double %call
}

define <2 x double> @test_rootn_afn_nnan_ninf_v2f64(<2 x double> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x double> @test_rootn_afn_nnan_ninf_v2f64(
; CHECK-SAME: <2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn <2 x double> @_Z5rootnDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x double> [[CALL]]
;
entry:
  %call = tail call nnan ninf afn <2 x double> @_Z5rootnDv2_dDv2_i(<2 x double> %x, <2 x i32> %y)
  ret <2 x double> %call
}

define half @test_rootn_afn_nnan_ninf_f16(half %x, i32 %y) {
; CHECK-LABEL: define half @test_rootn_afn_nnan_ninf_f16(
; CHECK-SAME: half [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn half @_Z5rootnDhi(half [[X]], i32 [[Y]])
; CHECK-NEXT:    ret half [[CALL]]
;
entry:
  %call = tail call nnan ninf afn half @_Z5rootnDhi(half %x, i32 %y)
  ret half %call
}

define <2 x half> @test_rootn_afn_nnan_ninf_v2f16(<2 x half> %x, <2 x i32> %y) {
; CHECK-LABEL: define <2 x half> @test_rootn_afn_nnan_ninf_v2f16(
; CHECK-SAME: <2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> [[Y]])
; CHECK-NEXT:    ret <2 x half> [[CALL]]
;
entry:
  %call = tail call nnan ninf afn <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y)
  ret <2 x half> %call
}

define float @test_rootn_fast_f32_nobuiltin(float %x, i32 %y) {
; CHECK-LABEL: define float @test_rootn_fast_f32_nobuiltin(
; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call fast float @_Z5rootnfi(float [[X]], i32 [[Y]]) #[[ATTR4]]
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call fast float @_Z5rootnfi(float %x, i32 %y) #0
  ret float %call
}

define float @test_rootn_fast_f32_strictfp(float %x, i32 %y) #1 {
; PRELINK-LABEL: define float @test_rootn_fast_f32_strictfp(
; PRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call fast float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]]) #[[ATTR0]]
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_fast_f32_strictfp(
; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP0:%.*]] = call fast float @llvm.experimental.constrained.sitofp.f32.i32(i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call fast float @llvm.experimental.constrained.fdiv.f32(float 1.000000e+00, float [[TMP0]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP3:%.*]] = call fast float @llvm.log2.f32(float [[TMP2]]) #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.experimental.constrained.fmul.f32(float [[TMP1]], float [[TMP3]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.exp2.f32(float [[TMP4]]) #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP6:%.*]] = and i32 [[Y]], 1
; NOPRELINK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select fast i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call fast float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]]) #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP9:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP10:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP9]], float +inf, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP11:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[X]], float 0.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
; NOPRELINK-NEXT:    [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
; NOPRELINK-NEXT:    [[TMP15:%.*]] = select fast i1 [[TMP14]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP16:%.*]] = select fast i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
; NOPRELINK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]]) #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP18:%.*]] = select fast i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
; NOPRELINK-NEXT:    [[TMP19:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[X]], float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR0]]
; NOPRELINK-NEXT:    [[TMP20:%.*]] = and i1 [[TMP19]], [[DOTNOT]]
; NOPRELINK-NEXT:    [[TMP21:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP22:%.*]] = or i1 [[TMP20]], [[TMP21]]
; NOPRELINK-NEXT:    [[TMP23:%.*]] = select fast i1 [[TMP22]], float +qnan, float [[TMP18]]
; NOPRELINK-NEXT:    ret float [[TMP23]]
;
entry:
  %call = tail call fast float @_Z5rootnfi(float %x, i32 %y) #1
  ret float %call
}

define float @test_rootn_fast_f32__y_poison(float %x) {
; PRELINK-LABEL: define float @test_rootn_fast_f32__y_poison(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[CALL:%.*]] = tail call fast float @_Z12__rootn_fastfi(float [[X]], i32 poison)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_fast_f32__y_poison(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    ret float poison
;
  %call = tail call fast float @_Z5rootnfi(float %x, i32 poison)
  ret float %call
}

define float @test_rootn_afn_nnan_ninf_f32__y_3(float %x) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_3(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[__ROOTN2CBRT:%.*]] = call nnan ninf afn float @_Z4cbrtf(float [[X]])
; PRELINK-NEXT:    ret float [[__ROOTN2CBRT]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_3(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], f0x3EAAAAAB
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
; NOPRELINK-NEXT:    ret float [[TMP9]]
;
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 3)
  ret float %call
}

define float @test_rootn_afn_nnan_ninf_f32__y_neg3(float %x) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg3(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 -3)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg3(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], f0xBEAAAAAB
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
; NOPRELINK-NEXT:    ret float [[TMP9]]
;
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -3)
  ret float %call
}

define float @test_rootn_afn_nnan_ninf_f32__y_4(float %x) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_4(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 4)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_4(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 2.500000e-01
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float 0.000000e+00, float [[TMP4]]
; NOPRELINK-NEXT:    [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float +qnan, float [[TMP6]]
; NOPRELINK-NEXT:    ret float [[TMP8]]
;
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 4)
  ret float %call
}

define float @test_rootn_afn_nnan_ninf_f32__y_neg4(float %x) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg4(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 -4)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg4(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], -2.500000e-01
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[TMP4]], float +inf
; NOPRELINK-NEXT:    [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float +qnan, float [[TMP6]]
; NOPRELINK-NEXT:    ret float [[TMP8]]
;
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -4)
  ret float %call
}

define float @test_rootn_afn_nnan_ninf_f32__y_5(float %x) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_5(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 5)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_5(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 2.000000e-01
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
; NOPRELINK-NEXT:    ret float [[TMP9]]
;
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 5)
  ret float %call
}

define float @test_rootn_afn_nnan_ninf_f32__y_neg5(float %x) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg5(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 -5)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg5(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], -2.000000e-01
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
; NOPRELINK-NEXT:    ret float [[TMP9]]
;
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -5)
  ret float %call
}

define float @test_rootn_afn_nnan_ninf_f32__y_7(float %x) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_7(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 7)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_7(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], f0x3E124925
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
; NOPRELINK-NEXT:    ret float [[TMP9]]
;
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 7)
  ret float %call
}

define float @test_rootn_afn_nnan_ninf_f32__y_neg7(float %x) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg7(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 -7)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg7(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], f0xBE124925
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
; NOPRELINK-NEXT:    ret float [[TMP9]]
;
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -7)
  ret float %call
}

define float @test_rootn_afn_nnan_ninf_f32__y_8(float %x) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_8(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 8)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_8(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 1.250000e-01
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float 0.000000e+00, float [[TMP4]]
; NOPRELINK-NEXT:    [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float +qnan, float [[TMP6]]
; NOPRELINK-NEXT:    ret float [[TMP8]]
;
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 8)
  ret float %call
}

define float @test_rootn_afn_nnan_ninf_f32__y_neg8(float %x) {
; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg8(
; PRELINK-SAME: float [[X:%.*]]) {
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 -8)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg8(
; NOPRELINK-SAME: float [[X:%.*]]) {
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], -1.250000e-01
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[TMP4]], float +inf
; NOPRELINK-NEXT:    [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float +qnan, float [[TMP6]]
; NOPRELINK-NEXT:    ret float [[TMP8]]
;
  %call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -8)
  ret float %call
}

define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_3(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_3(
; PRELINK-SAME: <2 x float> [[X:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[__ROOTN2CBRT:%.*]] = call nnan ninf afn <2 x float> @_Z4cbrtDv2_f(<2 x float> [[X]])
; PRELINK-NEXT:    ret <2 x float> [[__ROOTN2CBRT]]
;
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_3(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float f0x3EAAAAAB)
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP8]], <2 x float> [[TMP5]]
; NOPRELINK-NEXT:    ret <2 x float> [[TMP9]]
;
entry:
  %call = tail call afn nnan ninf <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 3, i32 3>)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_4(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_4(
; PRELINK-SAME: <2 x float> [[X:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 4))
; PRELINK-NEXT:    ret <2 x float> [[CALL]]
;
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_4(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 2.500000e-01)
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> [[TMP4]]
; NOPRELINK-NEXT:    [[TMP7:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP8:%.*]] = select nnan ninf afn <2 x i1> [[TMP7]], <2 x float> splat (float +qnan), <2 x float> [[TMP6]]
; NOPRELINK-NEXT:    ret <2 x float> [[TMP8]]
;
entry:
  %call = tail call afn nnan ninf <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 4, i32 4>)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg3(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg3(
; PRELINK-SAME: <2 x float> [[X:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -3))
; PRELINK-NEXT:    ret <2 x float> [[CALL]]
;
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg3(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float f0xBEAAAAAB)
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp nnan ninf afn une <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP5]], <2 x float> [[TMP8]]
; NOPRELINK-NEXT:    ret <2 x float> [[TMP9]]
;
entry:
  %call = tail call afn nnan ninf <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -3, i32 -3>)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg4(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg4(
; PRELINK-SAME: <2 x float> [[X:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -4))
; PRELINK-NEXT:    ret <2 x float> [[CALL]]
;
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg4(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float -2.500000e-01)
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = fcmp nnan ninf afn une <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> [[TMP4]], <2 x float> splat (float +inf)
; NOPRELINK-NEXT:    [[TMP7:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP8:%.*]] = select nnan ninf afn <2 x i1> [[TMP7]], <2 x float> splat (float +qnan), <2 x float> [[TMP6]]
; NOPRELINK-NEXT:    ret <2 x float> [[TMP8]]
;
entry:
  %call = tail call afn nnan ninf <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -4, i32 -4>)
  ret <2 x float> %call
}

define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_5(<2 x float> %x) {
; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_5(
; PRELINK-SAME: <2 x float> [[X:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 5))
; PRELINK-NEXT:    ret <2 x float> [[CALL]]
;
; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_5(
; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 2.000000e-01)
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP8]], <2 x float> [[TMP5]]
; NOPRELINK-NEXT:    ret <2 x float> [[TMP9]]
;
entry:
  %call = tail call afn nnan ninf <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 5, i32 5>)
  ret <2 x float> %call
}

define float @test_rootn_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) {
; CHECK-LABEL: define float @test_rootn_f32__x_known_positive(
; CHECK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 [[Y]])
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 %y)
  ret float %call
}

define float @test_rootn_afn_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) {
; PRELINK-LABEL: define float @test_rootn_afn_f32__x_known_positive(
; PRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call afn float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_f32__x_known_positive(
; NOPRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP0:%.*]] = sitofp afn i32 [[Y]] to float
; NOPRELINK-NEXT:    [[TMP1:%.*]] = fdiv nnan afn float 1.000000e+00, [[TMP0]]
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = call afn float @llvm.log2.f32(float [[TMP2]])
; NOPRELINK-NEXT:    [[TMP4:%.*]] = fmul afn float [[TMP1]], [[TMP3]]
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call afn float @llvm.exp2.f32(float [[TMP4]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = and i32 [[Y]], 1
; NOPRELINK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
; NOPRELINK-NEXT:    [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
; NOPRELINK-NEXT:    [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
; NOPRELINK-NEXT:    [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], +inf
; NOPRELINK-NEXT:    [[TMP11:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
; NOPRELINK-NEXT:    [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
; NOPRELINK-NEXT:    [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
; NOPRELINK-NEXT:    [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
; NOPRELINK-NEXT:    [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
; NOPRELINK-NEXT:    [[TMP19:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP20:%.*]] = select afn i1 [[TMP19]], float +qnan, float [[TMP18]]
; NOPRELINK-NEXT:    ret float [[TMP20]]
;
entry:
  %call = tail call afn float @_Z5rootnfi(float %x, i32 %y)
  ret float %call
}

define float @test_rootn_afn_ninf_nnan_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) {
; PRELINK-LABEL: define float @test_rootn_afn_ninf_nnan_f32__x_known_positive(
; PRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_ninf_nnan_f32__x_known_positive(
; NOPRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP0:%.*]] = sitofp nnan ninf afn i32 [[Y]] to float
; NOPRELINK-NEXT:    [[TMP1:%.*]] = fdiv nnan ninf afn float 1.000000e+00, [[TMP0]]
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP1]], [[TMP2]]
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = and i32 [[Y]], 1
; NOPRELINK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0
; NOPRELINK-NEXT:    [[TMP6:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
; NOPRELINK-NEXT:    [[TMP7:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[TMP6]])
; NOPRELINK-NEXT:    [[TMP8:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP9:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP10:%.*]] = xor i1 [[TMP8]], [[TMP9]]
; NOPRELINK-NEXT:    [[TMP11:%.*]] = select nnan ninf afn i1 [[TMP10]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP12:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
; NOPRELINK-NEXT:    [[TMP13:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP11]], float [[TMP12]])
; NOPRELINK-NEXT:    [[TMP14:%.*]] = select nnan ninf afn i1 [[TMP8]], float [[TMP13]], float [[TMP7]]
; NOPRELINK-NEXT:    [[TMP15:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP16:%.*]] = select nnan ninf afn i1 [[TMP15]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT:    ret float [[TMP16]]
;
entry:
  %call = tail call afn ninf nnan float @_Z5rootnfi(float %x, i32 %y)
  ret float %call
}

define float @test_rootn_afn_f32__x_known_positive__y_4(float nofpclass(ninf nsub nnorm) %x) {
; PRELINK-LABEL: define float @test_rootn_afn_f32__x_known_positive__y_4(
; PRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[CALL:%.*]] = tail call afn float @_Z12__rootn_fastfi(float [[X]], i32 4)
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_rootn_afn_f32__x_known_positive__y_4(
; NOPRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[TMP0:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.log2.f32(float [[TMP0]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = fmul afn float [[TMP1]], 2.500000e-01
; NOPRELINK-NEXT:    [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call afn float @llvm.fabs.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], +inf
; NOPRELINK-NEXT:    [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP8:%.*]] = select i1 [[TMP6]], float +inf, float [[TMP4]]
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select i1 [[TMP7]], float 0.000000e+00, float [[TMP8]]
; NOPRELINK-NEXT:    ret float [[TMP9]]
;
entry:
  %call = tail call afn float @_Z5rootnfi(float %x, i32 4)
  ret float %call
}

define float @test_rootn_f32__x_known_positive__y_4(float nofpclass(ninf nsub nnorm) %x) {
; CHECK-LABEL: define float @test_rootn_f32__x_known_positive__y_4(
; CHECK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 4)
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %call = tail call float @_Z5rootnfi(float %x, i32 4)
  ret float %call
}

define float @test_rootn_f32_y_known_even(float %x, i32 %y.arg) {
; CHECK-LABEL: define float @test_rootn_f32_y_known_even(
; CHECK-SAME: float [[X:%.*]], i32 [[Y_ARG:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[Y:%.*]] = shl i32 [[Y_ARG]], 1
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 [[Y]])
; CHECK-NEXT:    ret float [[CALL]]
;
entry:
  %y = shl i32 %y.arg, 1
  %call = tail call float @_Z5rootnfi(float %x, i32 %y)
  ret float %call
}

define float @test_fast_rootn_f32_y_known_even(float %x, i32 %y.arg) {
; PRELINK-LABEL: define float @test_fast_rootn_f32_y_known_even(
; PRELINK-SAME: float [[X:%.*]], i32 [[Y_ARG:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[Y:%.*]] = shl i32 [[Y_ARG]], 1
; PRELINK-NEXT:    [[CALL:%.*]] = tail call fast float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_fast_rootn_f32_y_known_even(
; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y_ARG:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[Y:%.*]] = shl i32 [[Y_ARG]], 1
; NOPRELINK-NEXT:    [[TMP0:%.*]] = sitofp fast i32 [[Y]] to float
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = call fast float @llvm.log2.f32(float [[TMP2]])
; NOPRELINK-NEXT:    [[TMP4:%.*]] = fdiv fast float [[TMP3]], [[TMP0]]
; NOPRELINK-NEXT:    [[TMP5:%.*]] = call fast float @llvm.exp2.f32(float [[TMP4]])
; NOPRELINK-NEXT:    [[TMP6:%.*]] = fcmp fast oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP7:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP8:%.*]] = xor i1 [[TMP6]], [[TMP7]]
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select fast i1 [[TMP8]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP10:%.*]] = select fast i1 [[TMP6]], float [[TMP9]], float [[TMP5]]
; NOPRELINK-NEXT:    [[TMP11:%.*]] = fcmp fast olt float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP12:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
; NOPRELINK-NEXT:    [[TMP14:%.*]] = select fast i1 [[TMP13]], float +qnan, float [[TMP10]]
; NOPRELINK-NEXT:    ret float [[TMP14]]
;
entry:
  %y = shl i32 %y.arg, 1
  %call = tail call fast float @_Z5rootnfi(float %x, i32 %y)
  ret float %call
}

define float @test_fast_rootn_f32_known_positive_y_known_even(float nofpclass(ninf nsub nnorm) %x, i32 %y.arg) {
; PRELINK-LABEL: define float @test_fast_rootn_f32_known_positive_y_known_even(
; PRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y_ARG:%.*]]) {
; PRELINK-NEXT:  entry:
; PRELINK-NEXT:    [[Y:%.*]] = shl i32 [[Y_ARG]], 1
; PRELINK-NEXT:    [[CALL:%.*]] = tail call fast float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
; PRELINK-NEXT:    ret float [[CALL]]
;
; NOPRELINK-LABEL: define float @test_fast_rootn_f32_known_positive_y_known_even(
; NOPRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y_ARG:%.*]]) {
; NOPRELINK-NEXT:  entry:
; NOPRELINK-NEXT:    [[Y:%.*]] = shl i32 [[Y_ARG]], 1
; NOPRELINK-NEXT:    [[TMP0:%.*]] = sitofp fast i32 [[Y]] to float
; NOPRELINK-NEXT:    [[TMP1:%.*]] = call fast float @llvm.fabs.f32(float [[X]])
; NOPRELINK-NEXT:    [[TMP2:%.*]] = call fast float @llvm.log2.f32(float [[TMP1]])
; NOPRELINK-NEXT:    [[TMP3:%.*]] = fdiv fast float [[TMP2]], [[TMP0]]
; NOPRELINK-NEXT:    [[TMP4:%.*]] = call fast float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT:    [[TMP5:%.*]] = fcmp fast oeq float [[X]], 0.000000e+00
; NOPRELINK-NEXT:    [[TMP6:%.*]] = icmp slt i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP7:%.*]] = xor i1 [[TMP5]], [[TMP6]]
; NOPRELINK-NEXT:    [[TMP8:%.*]] = select fast i1 [[TMP7]], float 0.000000e+00, float +inf
; NOPRELINK-NEXT:    [[TMP9:%.*]] = select fast i1 [[TMP5]], float [[TMP8]], float [[TMP4]]
; NOPRELINK-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[Y]], 0
; NOPRELINK-NEXT:    [[TMP11:%.*]] = select fast i1 [[TMP10]], float +qnan, float [[TMP9]]
; NOPRELINK-NEXT:    ret float [[TMP11]]
;
entry:
  %y = shl i32 %y.arg, 1
  %call = tail call fast float @_Z5rootnfi(float %x, i32 %y)
  ret float %call
}

define float @test_rootn_f32__y_0_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_0_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 0) #[[ATTR4]]
; CHECK-NEXT:    ret float [[CALL]]
;
  %call = tail call float @_Z5rootnfi(float %x, i32 0) #0
  ret float %call
}

define float @test_rootn_f32__y_1_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_1_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 1) #[[ATTR4]]
; CHECK-NEXT:    ret float [[CALL]]
;
  %call = tail call float @_Z5rootnfi(float %x, i32 1) #0
  ret float %call
}

define float @test_rootn_f32__y_2_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_2_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 2) #[[ATTR4]]
; CHECK-NEXT:    ret float [[CALL]]
;
  %call = tail call float @_Z5rootnfi(float %x, i32 2) #0
  ret float %call
}

define float @test_rootn_f32__y_3_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_3_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 3) #[[ATTR4]]
; CHECK-NEXT:    ret float [[CALL]]
;
  %call = tail call float @_Z5rootnfi(float %x, i32 3) #0
  ret float %call
}

define float @test_rootn_f32__y_neg1_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg1_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -1) #[[ATTR4]]
; CHECK-NEXT:    ret float [[CALL]]
;
  %call = tail call float @_Z5rootnfi(float %x, i32 -1) #0
  ret float %call
}

define float @test_rootn_f32__y_neg2_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg2_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT:    [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2) #[[ATTR4]]
; CHECK-NEXT:    ret float [[CALL]]
;
  %call = tail call float @_Z5rootnfi(float %x, i32 -2) #0
  ret float %call
}

attributes #0 = { nobuiltin }
attributes #1 = { strictfp }
attributes #2 = { noinline }

!llvm.module.flags = !{!1}

!0 = !{float 3.0}
!1 = !{i32 1, !"amdgpu-libcall-have-fast-pow", i32 1}

;.
; PRELINK: attributes #[[ATTR0]] = { strictfp }
; PRELINK: attributes #[[ATTR1:[0-9]+]] = { nounwind memory(read) }
; PRELINK: attributes #[[ATTR2:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
; PRELINK: attributes #[[ATTR3]] = { noinline }
; PRELINK: attributes #[[ATTR4]] = { nobuiltin }
;.
; NOPRELINK: attributes #[[ATTR0]] = { strictfp }
; NOPRELINK: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
; NOPRELINK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
; NOPRELINK: attributes #[[ATTR3]] = { noinline }
; NOPRELINK: attributes #[[ATTR4]] = { nobuiltin }
;.
; PRELINK: [[META0:![0-9]+]] = !{i32 1, !"amdgpu-libcall-have-fast-pow", i32 1}
; PRELINK: [[META1]] = !{float 2.000000e+00}
; PRELINK: [[META2]] = !{float 3.000000e+00}
;.
; NOPRELINK: [[META0:![0-9]+]] = !{i32 1, !"amdgpu-libcall-have-fast-pow", i32 1}
; NOPRELINK: [[META1]] = !{float 2.000000e+00}
; NOPRELINK: [[META2]] = !{float 3.000000e+00}
;.