llvm/test/CodeGen/Xtensa/rem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=XTENSA %s
; RUN: llc -mtriple=xtensa -mattr=+div32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=XTENSA-DIV %s

define i32 @srem(i32 signext %a0, i32 signext %a1) nounwind readnone {
; XTENSA-LABEL: srem:
; XTENSA:       # %bb.0: # %entry
; XTENSA-NEXT:    addi a8, a1, -16
; XTENSA-NEXT:    or a1, a8, a8
; XTENSA-NEXT:    s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT:    l32r a8, .LCPI0_0
; XTENSA-NEXT:    callx0 a8
; XTENSA-NEXT:    l32i a0, a1, 0 # 4-byte Folded Reload
; XTENSA-NEXT:    addi a8, a1, 16
; XTENSA-NEXT:    or a1, a8, a8
; XTENSA-NEXT:    ret
;
; XTENSA-DIV-LABEL: srem:
; XTENSA-DIV:       # %bb.0: # %entry
; XTENSA-DIV-NEXT:    rems a2, a2, a3
; XTENSA-DIV-NEXT:    ret
entry:
  %rem = srem i32 %a0, %a1
  ret i32 %rem
}

define i32 @urem(i32 signext %a0, i32 signext %a1) nounwind readnone {
; XTENSA-LABEL: urem:
; XTENSA:       # %bb.0: # %entry
; XTENSA-NEXT:    addi a8, a1, -16
; XTENSA-NEXT:    or a1, a8, a8
; XTENSA-NEXT:    s32i a0, a1, 0 # 4-byte Folded Spill
; XTENSA-NEXT:    l32r a8, .LCPI1_0
; XTENSA-NEXT:    callx0 a8
; XTENSA-NEXT:    l32i a0, a1, 0 # 4-byte Folded Reload
; XTENSA-NEXT:    addi a8, a1, 16
; XTENSA-NEXT:    or a1, a8, a8
; XTENSA-NEXT:    ret
;
; XTENSA-DIV-LABEL: urem:
; XTENSA-DIV:       # %bb.0: # %entry
; XTENSA-DIV-NEXT:    remu a2, a2, a3
; XTENSA-DIV-NEXT:    ret
entry:
  %rem = urem i32 %a0, %a1
  ret i32 %rem
}