llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv64 -mattr='+v' < %s | FileCheck %s

define <2 x i8> @fp4(<4 x i4> %0) nounwind {
; CHECK-LABEL: fp4:
; CHECK:       # %bb.0:
; CHECK-NEXT:    addi sp, sp, -16
; CHECK-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    vslidedown.vi v9, v8, 1
; CHECK-NEXT:    vmv.x.s a1, v9
; CHECK-NEXT:    vslidedown.vi v9, v8, 2
; CHECK-NEXT:    vslidedown.vi v8, v8, 3
; CHECK-NEXT:    andi a0, a0, 15
; CHECK-NEXT:    vmv.x.s a2, v9
; CHECK-NEXT:    andi a1, a1, 15
; CHECK-NEXT:    slli a1, a1, 4
; CHECK-NEXT:    or a0, a0, a1
; CHECK-NEXT:    vmv.x.s a1, v8
; CHECK-NEXT:    andi a2, a2, 15
; CHECK-NEXT:    slli a1, a1, 12
; CHECK-NEXT:    slli a2, a2, 8
; CHECK-NEXT:    or a1, a2, a1
; CHECK-NEXT:    or a0, a0, a1
; CHECK-NEXT:    sh a0, 14(sp)
; CHECK-NEXT:    addi a0, sp, 14
; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT:    vle8.v v8, (a0)
; CHECK-NEXT:    addi sp, sp, 16
; CHECK-NEXT:    ret
  %2 = bitcast <4 x i4> %0 to <2 x i8>
  ret <2 x i8> %2
}