llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.gfx1250.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
; RUN: llc -global-isel=1 -amdgpu-load-store-vectorizer=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s

define amdgpu_kernel void @v_permlane_bcast_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {
; GFX1250-LABEL: v_permlane_bcast_b32_vss:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_xcnt 0x0
; GFX1250-NEXT:    s_load_b32 s4, s[4:5], 0x34
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_bcast_b32 v0, v0, s3, s4
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.bcast(i32 %src0, i32 %src1, i32 %src2)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_bcast_b32_vii(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_bcast_b32_vii:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_bcast_b32 v0, v0, 1, 2
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.bcast(i32 %src0, i32 1, i32 2)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_bcast_b32_vll(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_bcast_b32_vll:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_movk_i32 s2, 0x64
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    v_permlane_bcast_b32 v0, v0, s2, 0x66
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.bcast(i32 %src0, i32 100, i32 102)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_bcast_b32_vvv(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-SDAG-LABEL: v_permlane_bcast_b32_vvv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-SDAG-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-SDAG-NEXT:    v_bfe_u32 v0, v0, 10, 10
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v1, s2
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-SDAG-NEXT:    v_permlane_bcast_b32 v1, v1, s3, s2
; GFX1250-SDAG-NEXT:    global_store_b32 v0, v1, s[0:1]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: v_permlane_bcast_b32_vvv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-GISEL-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-GISEL-NEXT:    v_bfe_u32 v0, v0, 10, 10
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-GISEL-NEXT:    s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_permlane_bcast_b32 v0, v0, s3, s4
; GFX1250-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-GISEL-NEXT:    s_endpgm
  %tidx = call i32 @llvm.amdgcn.workitem.id.x()
  %tidy = call i32 @llvm.amdgcn.workitem.id.y()
  %v = call i32 @llvm.amdgcn.permlane.bcast(i32 %src0, i32 %tidx, i32 %tidy)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_down_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {
; GFX1250-LABEL: v_permlane_down_b32_vss:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_xcnt 0x0
; GFX1250-NEXT:    s_load_b32 s4, s[4:5], 0x34
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_down_b32 v0, v0, s3, s4
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.down(i32 %src0, i32 %src1, i32 %src2)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_down_b32_vii(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_down_b32_vii:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_down_b32 v0, v0, 1, 2
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.down(i32 %src0, i32 1, i32 2)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_down_b32_vll(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_down_b32_vll:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_movk_i32 s2, 0x64
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    v_permlane_down_b32 v0, v0, s2, 0x66
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.down(i32 %src0, i32 100, i32 102)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_down_b32_vvv(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-SDAG-LABEL: v_permlane_down_b32_vvv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-SDAG-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-SDAG-NEXT:    v_bfe_u32 v0, v0, 10, 10
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v1, s2
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-SDAG-NEXT:    v_permlane_down_b32 v1, v1, s3, s2
; GFX1250-SDAG-NEXT:    global_store_b32 v0, v1, s[0:1]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: v_permlane_down_b32_vvv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-GISEL-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-GISEL-NEXT:    v_bfe_u32 v0, v0, 10, 10
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-GISEL-NEXT:    s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_permlane_down_b32 v0, v0, s3, s4
; GFX1250-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-GISEL-NEXT:    s_endpgm
  %tidx = call i32 @llvm.amdgcn.workitem.id.x()
  %tidy = call i32 @llvm.amdgcn.workitem.id.y()
  %v = call i32 @llvm.amdgcn.permlane.down(i32 %src0, i32 %tidx, i32 %tidy)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_up_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {
; GFX1250-LABEL: v_permlane_up_b32_vss:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_xcnt 0x0
; GFX1250-NEXT:    s_load_b32 s4, s[4:5], 0x34
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_up_b32 v0, v0, s3, s4
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.up(i32 %src0, i32 %src1, i32 %src2)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_up_b32_vii(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_up_b32_vii:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_up_b32 v0, v0, 1, 2
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.up(i32 %src0, i32 1, i32 2)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_up_b32_vll(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_up_b32_vll:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_movk_i32 s2, 0x64
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    v_permlane_up_b32 v0, v0, s2, 0x66
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.up(i32 %src0, i32 100, i32 102)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_up_b32_vvv(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-SDAG-LABEL: v_permlane_up_b32_vvv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-SDAG-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-SDAG-NEXT:    v_bfe_u32 v0, v0, 10, 10
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v1, s2
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-SDAG-NEXT:    v_permlane_up_b32 v1, v1, s3, s2
; GFX1250-SDAG-NEXT:    global_store_b32 v0, v1, s[0:1]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: v_permlane_up_b32_vvv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-GISEL-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-GISEL-NEXT:    v_bfe_u32 v0, v0, 10, 10
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-GISEL-NEXT:    s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_permlane_up_b32 v0, v0, s3, s4
; GFX1250-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-GISEL-NEXT:    s_endpgm
  %tidx = call i32 @llvm.amdgcn.workitem.id.x()
  %tidy = call i32 @llvm.amdgcn.workitem.id.y()
  %v = call i32 @llvm.amdgcn.permlane.up(i32 %src0, i32 %tidx, i32 %tidy)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_xor_b32_vss(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {
; GFX1250-LABEL: v_permlane_xor_b32_vss:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_xcnt 0x0
; GFX1250-NEXT:    s_load_b32 s4, s[4:5], 0x34
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_xor_b32 v0, v0, s3, s4
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.xor(i32 %src0, i32 %src1, i32 %src2)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_xor_b32_vii(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_xor_b32_vii:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_xor_b32 v0, v0, 1, 2
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.xor(i32 %src0, i32 1, i32 2)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_xor_b32_vll(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_xor_b32_vll:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_movk_i32 s2, 0x64
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    v_permlane_xor_b32 v0, v0, s2, 0x66
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.xor(i32 %src0, i32 100, i32 102)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_xor_b32_vvv(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-SDAG-LABEL: v_permlane_xor_b32_vvv:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-SDAG-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-SDAG-NEXT:    v_bfe_u32 v0, v0, 10, 10
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v1, s2
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-SDAG-NEXT:    v_permlane_xor_b32 v1, v1, s3, s2
; GFX1250-SDAG-NEXT:    global_store_b32 v0, v1, s[0:1]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: v_permlane_xor_b32_vvv:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-GISEL-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
; GFX1250-GISEL-NEXT:    v_bfe_u32 v0, v0, 10, 10
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-GISEL-NEXT:    s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    v_permlane_xor_b32 v0, v0, s3, s4
; GFX1250-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-GISEL-NEXT:    s_endpgm
  %tidx = call i32 @llvm.amdgcn.workitem.id.x()
  %tidy = call i32 @llvm.amdgcn.workitem.id.y()
  %v = call i32 @llvm.amdgcn.permlane.xor(i32 %src0, i32 %tidx, i32 %tidy)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_idx_gen_b32_vs(ptr addrspace(1) %out, i32 %src0, i32 %src1) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vs:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_idx_gen_b32 v0, v0, s3
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %src0, i32 %src1)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_idx_gen_b32_vi(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vi:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_idx_gen_b32 v0, v0, 1
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %src0, i32 1)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_idx_gen_b32_vl(ptr addrspace(1) %out, i32 %src0) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vl:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT:    v_permlane_idx_gen_b32 v0, v0, 0x64
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %src0, i32 100)
  store i32 %v, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @v_permlane_idx_gen_b32_vv(ptr addrspace(1) %out) {
; GFX1250-LABEL: v_permlane_idx_gen_b32_vv:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX1250-NEXT:    v_bfe_u32 v1, v0, 10, 10
; GFX1250-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-NEXT:    v_readfirstlane_b32 s2, v1
; GFX1250-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-NEXT:    v_permlane_idx_gen_b32 v0, v0, s2
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-NEXT:    s_endpgm
  %tidx = call i32 @llvm.amdgcn.workitem.id.x()
  %tidy = call i32 @llvm.amdgcn.workitem.id.y()
  %v = call i32 @llvm.amdgcn.permlane.idx.gen(i32 %tidx, i32 %tidy)
  store i32 %v, ptr addrspace(1) %out
  ret void
}