llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250,GFX1250-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 < %s | FileCheck -check-prefixes=GCN,GFX1251,GFX1251-SDAG %s

; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250,GFX1250-GISEL %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1251 < %s | FileCheck -check-prefixes=GCN,GFX1251,GFX1251-GISEL %s

; this test has both gfx1250/1251 run lines to check availability of the intrinsic on both variants.

; test behavior with unsupported 'consume' and 'acq_rel' ordering

define i32 @test_load_consume(ptr noundef readonly %addr)  {
; GCN-LABEL: test_load_consume:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    flat_load_b32 v0, v[0:1] scope:SCOPE_SYS
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_set_pc_i64 s[30:31]
entry:
  %0 = tail call i32 @llvm.amdgcn.cooperative.atomic.load.32x4B.p0(ptr %addr, i32 1, metadata !0)
  ret i32 %0
}

define i32 @test_load_acqrel(ptr noundef readonly %addr)  {
; GCN-LABEL: test_load_acqrel:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    flat_load_b32 v0, v[0:1] scope:SCOPE_SYS
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_set_pc_i64 s[30:31]
entry:
  %0 = tail call i32 @llvm.amdgcn.cooperative.atomic.load.32x4B.p0(ptr %addr, i32 4, metadata !0)
  ret i32 %0
}

define void @test_store_acqrel(ptr noundef %addr, i32 noundef %val)  {
; GCN-LABEL: test_store_acqrel:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    flat_store_b32 v[0:1], v2 scope:SCOPE_SYS
; GCN-NEXT:    s_wait_dscnt 0x0
; GCN-NEXT:    s_set_pc_i64 s[30:31]
entry:
  tail call void @llvm.amdgcn.cooperative.atomic.store.32x4B.p0(ptr %addr, i32 %val, i32 4, metadata !0)
  ret void
}

!0 = !{ !"" }

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1250: {{.*}}
; GFX1250-GISEL: {{.*}}
; GFX1250-SDAG: {{.*}}
; GFX1251: {{.*}}
; GFX1251-GISEL: {{.*}}
; GFX1251-SDAG: {{.*}}