llvm/test/CodeGen/X86/callbr-asm-different-indirect-target-end-to-end.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=x86_64-- -O1 < %s | FileCheck %s

define i64 @inlineasm_br_different_indirect_target(i1 %cmp) {
; CHECK-LABEL: inlineasm_br_different_indirect_target:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xorl %eax, %eax
; CHECK-NEXT:  .LBB0_1: # Inline asm indirect target
; CHECK-NEXT:    # %loop
; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    # Label of block must be emitted
; CHECK-NEXT:    testb $1, %dil
; CHECK-NEXT:    je .LBB0_1
; CHECK-NEXT:  # %bb.2: # %loop.end
; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT:    xorq $9, %rax
; CHECK-NEXT:    #APP
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:  # %bb.3: # %exit
; CHECK-NEXT:    retq
entry:
  br label %loop

loop:                                             ; preds = %loop.end, %loop, %entry
  %val = phi i64 [ 0, %entry ], [ %val.next, %loop.end ], [ poison, %loop ]
  br i1 %cmp, label %loop.end, label %loop

loop.end:                                         ; preds = %loop
  %val.next = xor i64 %val, 9
  callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"()
          to label %exit [label %loop]

exit:                                             ; preds = %loop.end
  ret i64 %val.next
}