llvm/test/CodeGen/ARM/cls.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=armv5 %s -o - | FileCheck %s --check-prefixes=CHECKV5
; RUN: llc -mtriple=thumbv8.1m.main %s -o - | FileCheck %s --check-prefix=CHECKV8

define i32 @cls(i32 %t) {
; CHECKV5-LABEL: cls:
; CHECKV5:       @ %bb.0:
; CHECKV5-NEXT:    eor r0, r0, r0, asr #31
; CHECKV5-NEXT:    mov r1, #1
; CHECKV5-NEXT:    orr r0, r1, r0, lsl #1
; CHECKV5-NEXT:    clz r0, r0
; CHECKV5-NEXT:    bx lr
;
; CHECKV8-LABEL: cls:
; CHECKV8:       @ %bb.0:
; CHECKV8-NEXT:    eor.w r0, r0, r0, asr #31
; CHECKV8-NEXT:    lsls r0, r0, #1
; CHECKV8-NEXT:    adds r0, #1
; CHECKV8-NEXT:    clz r0, r0
; CHECKV8-NEXT:    bx lr
  %cls.i = call i32 @llvm.arm.cls(i32 %t)
  ret i32 %cls.i
}

define i32 @cls64(i64 %t) {
; CHECKV5-LABEL: cls64:
; CHECKV5:       @ %bb.0:
; CHECKV5-NEXT:    cmp r1, #0
; CHECKV5-NEXT:    mvnmi r0, r0
; CHECKV5-NEXT:    clz r2, r0
; CHECKV5-NEXT:    eor r0, r1, r1, asr #31
; CHECKV5-NEXT:    mov r1, #1
; CHECKV5-NEXT:    orr r0, r1, r0, lsl #1
; CHECKV5-NEXT:    clz r0, r0
; CHECKV5-NEXT:    cmp r0, #31
; CHECKV5-NEXT:    addeq r0, r2, #31
; CHECKV5-NEXT:    bx lr
;
; CHECKV8-LABEL: cls64:
; CHECKV8:       @ %bb.0:
; CHECKV8-NEXT:    cmp r1, #0
; CHECKV8-NEXT:    cinv r0, r0, mi
; CHECKV8-NEXT:    clz r2, r0
; CHECKV8-NEXT:    eor.w r0, r1, r1, asr #31
; CHECKV8-NEXT:    lsls r0, r0, #1
; CHECKV8-NEXT:    adds r0, #1
; CHECKV8-NEXT:    clz r0, r0
; CHECKV8-NEXT:    cmp r0, #31
; CHECKV8-NEXT:    it eq
; CHECKV8-NEXT:    addeq.w r0, r2, #31
; CHECKV8-NEXT:    bx lr
  %cls.i = call i32 @llvm.arm.cls64(i64 %t)
  ret i32 %cls.i
}