llvm/test/CodeGen/RISCV/xqcibi-redundant-copy-elim.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+xqcibi -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV32IXQCIBI
; RUN: llc -mtriple=riscv32 -mattr=+xqcibi,+xqcili -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV32IXQCIBILI

define dso_local i32 @test_beqi(i32 %a) nounwind {
; RV32I-LABEL: test_beqi:
; RV32I:       # %bb.0: # %entry
; RV32I-NEXT:    li a1, 7
; RV32I-NEXT:    bne a0, a1, .LBB0_2
; RV32I-NEXT:  # %bb.1: # %if.end
; RV32I-NEXT:    li a0, 7
; RV32I-NEXT:    ret
; RV32I-NEXT:  .LBB0_2: # %if.then
; RV32I-NEXT:    li a0, 1
; RV32I-NEXT:    ret
;
; RV32IXQC-LABEL: test_beqi:
; RV32IXQC:       # %bb.0: # %entry
; RV32IXQC-NEXT:    qc.beqi a0, 7, .LBB0_2
; RV32IXQC-NEXT:  # %bb.1: # %if.then
; RV32IXQC-NEXT:    li a0, 1
; RV32IXQC-NEXT:  .LBB0_2: # %if.end
; RV32IXQC-NEXT:    ret
entry:
  %cmp = icmp eq i32 %a, 7
  br i1 %cmp, label %if.end, label %if.then

if.then:
  ret i32 1
if.end:
  ret i32 7
}

define dso_local i32 @test_e_beqi(i32 %a) nounwind {
; RV32I-LABEL: test_e_beqi:
; RV32I:       # %bb.0: # %entry
; RV32I-NEXT:    li a1, 40
; RV32I-NEXT:    bne a0, a1, .LBB1_2
; RV32I-NEXT:  # %bb.1: # %if.end
; RV32I-NEXT:    li a0, 40
; RV32I-NEXT:    ret
; RV32I-NEXT:  .LBB1_2: # %if.then
; RV32I-NEXT:    li a0, 1
; RV32I-NEXT:    ret
;
; RV32IXQC-LABEL: test_e_beqi:
; RV32IXQC:       # %bb.0: # %entry
; RV32IXQC-NEXT:    qc.e.beqi a0, 40, .LBB1_2
; RV32IXQC-NEXT:  # %bb.1: # %if.then
; RV32IXQC-NEXT:    li a0, 1
; RV32IXQC-NEXT:  .LBB1_2: # %if.end
; RV32IXQC-NEXT:    ret
entry:
  %cmp = icmp eq i32 %a, 40
  br i1 %cmp, label %if.end, label %if.then

if.then:
  ret i32 1
if.end:
  ret i32 40
}

define dso_local i32 @test_e_beqi_li(i32 %a) nounwind {
; RV32I-LABEL: test_e_beqi_li:
; RV32I:       # %bb.0: # %entry
; RV32I-NEXT:    lui a1, 1
; RV32I-NEXT:    addi a1, a1, -96
; RV32I-NEXT:    bne a0, a1, .LBB2_2
; RV32I-NEXT:  # %bb.1: # %if.end
; RV32I-NEXT:    mv a0, a1
; RV32I-NEXT:    ret
; RV32I-NEXT:  .LBB2_2: # %if.then
; RV32I-NEXT:    li a0, 1
; RV32I-NEXT:    ret
;
; RV32IXQCIBI-LABEL: test_e_beqi_li:
; RV32IXQCIBI:       # %bb.0: # %entry
; RV32IXQCIBI-NEXT:    qc.e.bnei a0, 4000, .LBB2_2
; RV32IXQCIBI-NEXT:  # %bb.1: # %if.end
; RV32IXQCIBI-NEXT:    lui a0, 1
; RV32IXQCIBI-NEXT:    addi a0, a0, -96
; RV32IXQCIBI-NEXT:    ret
; RV32IXQCIBI-NEXT:  .LBB2_2: # %if.then
; RV32IXQCIBI-NEXT:    li a0, 1
; RV32IXQCIBI-NEXT:    ret
;
; RV32IXQCIBILI-LABEL: test_e_beqi_li:
; RV32IXQCIBILI:       # %bb.0: # %entry
; RV32IXQCIBILI-NEXT:    qc.e.beqi a0, 4000, .LBB2_2
; RV32IXQCIBILI-NEXT:  # %bb.1: # %if.then
; RV32IXQCIBILI-NEXT:    li a0, 1
; RV32IXQCIBILI-NEXT:  .LBB2_2: # %if.end
; RV32IXQCIBILI-NEXT:    ret
entry:
  %cmp = icmp eq i32 %a, 4000
  br i1 %cmp, label %if.end, label %if.then

if.then:
  ret i32 1
if.end:
  ret i32 4000
}