llvm/test/CodeGen/RISCV/xandesperf-redundant-copy-elim.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV32IXANDESPERF

define i32 @test_beqc(i32 %a) nounwind {
; RV32I-LABEL: test_beqc:
; RV32I:       # %bb.0: # %entry
; RV32I-NEXT:    li a1, 7
; RV32I-NEXT:    bne a0, a1, .LBB0_2
; RV32I-NEXT:  # %bb.1: # %if.end
; RV32I-NEXT:    li a0, 7
; RV32I-NEXT:    ret
; RV32I-NEXT:  .LBB0_2: # %if.then
; RV32I-NEXT:    li a0, 1
; RV32I-NEXT:    ret
;
; RV32IXANDESPERF-LABEL: test_beqc:
; RV32IXANDESPERF:       # %bb.0: # %entry
; RV32IXANDESPERF-NEXT:    nds.beqc a0, 7, .LBB0_2
; RV32IXANDESPERF-NEXT:  # %bb.1: # %if.then
; RV32IXANDESPERF-NEXT:    li a0, 1
; RV32IXANDESPERF-NEXT:  .LBB0_2: # %if.end
; RV32IXANDESPERF-NEXT:    ret
entry:
  %cmp = icmp eq i32 %a, 7
  br i1 %cmp, label %if.end, label %if.then
if.then:
  ret i32 1
if.end:
  ret i32 7
}

define i32 @test_bnec(i32 %a) nounwind {
; RV32I-LABEL: test_bnec:
; RV32I:       # %bb.0: # %entry
; RV32I-NEXT:    li a1, 7
; RV32I-NEXT:    beq a0, a1, .LBB1_2
; RV32I-NEXT:  # %bb.1: # %if.end
; RV32I-NEXT:    li a0, 1
; RV32I-NEXT:    ret
; RV32I-NEXT:  .LBB1_2: # %if.then
; RV32I-NEXT:    li a0, 7
; RV32I-NEXT:    ret
;
; RV32IXANDESPERF-LABEL: test_bnec:
; RV32IXANDESPERF:       # %bb.0: # %entry
; RV32IXANDESPERF-NEXT:    nds.beqc a0, 7, .LBB1_2
; RV32IXANDESPERF-NEXT:  # %bb.1: # %if.end
; RV32IXANDESPERF-NEXT:    li a0, 1
; RV32IXANDESPERF-NEXT:    ret
; RV32IXANDESPERF-NEXT:  .LBB1_2: # %if.then
; RV32IXANDESPERF-NEXT:    ret
entry:
  %cmp = icmp ne i32 %a, 7
  br i1 %cmp, label %if.end, label %if.then
if.then:
  ret i32 7
if.end:
  ret i32 1
}