llvm/test/CodeGen/RISCV/rvv/vl-optimizer-subreg-assert.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -o - %s | FileCheck %s
# Check that there is no assert on subregister uses.

---
name: vl_optimizer_subreg_assert
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $v8m2

    ; CHECK-LABEL: name: vl_optimizer_subreg_assert
    ; CHECK: liveins: $v8m2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vmv0 = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
    ; CHECK-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 $noreg, killed [[DEF2]], [[DEF]], [[DEF1]], -1, 6 /* e64 */
    ; CHECK-NEXT: [[PseudoVREDMAXU_VS_M8_E64_:%[0-9]+]]:vr = PseudoVREDMAXU_VS_M8_E64 $noreg, [[PseudoVMERGE_VVM_M8_]], [[PseudoVMERGE_VVM_M8_]].sub_vrm1_0, -1, 6 /* e64 */, 1 /* ta, mu */
    ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S killed [[PseudoVREDMAXU_VS_M8_E64_]], 6 /* e64 */
    ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:vrm8nov0 = IMPLICIT_DEF
    %1:vmv0 = IMPLICIT_DEF
    %2:vrm8nov0 = IMPLICIT_DEF
    %3:vrm8nov0 = PseudoVMERGE_VVM_M8 $noreg, killed %2, %0, %1, -1, 6 /* e64 */
    %4:vr = PseudoVREDMAXU_VS_M8_E64 $noreg, %3, %3.sub_vrm1_0, -1, 6 /* e64 */, 1 /* ta, mu */
    %5:gpr = PseudoVMV_X_S killed %4, 6 /* e64 */
    $x10 = COPY %5
    PseudoRET implicit $x10

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