llvm/test/CodeGen/RISCV/rvv/vfrsub-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa,+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa,+v -verify-machineinstrs < %s | FileCheck %s

define <vscale x 1 x bfloat> @vrsub_vf_nxv1bf16(<vscale x 1 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vrsub_vf_nxv1bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfrsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 1 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <vscale x 1 x bfloat> %head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer
  %vc = fsub <vscale x 1 x bfloat> %splat, %va
  ret <vscale x 1 x bfloat> %vc
}

define <vscale x 2 x bfloat> @vrsub_vf_nxv2bf16(<vscale x 2 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vrsub_vf_nxv2bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16alt, mf2, ta, ma
; CHECK-NEXT:    vfrsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 2 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <vscale x 2 x bfloat> %head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer
  %vc = fsub <vscale x 2 x bfloat> %splat, %va
  ret <vscale x 2 x bfloat> %vc
}

define <vscale x 4 x bfloat> @vrsub_vf_nxv4bf16(<vscale x 4 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vrsub_vf_nxv4bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16alt, m1, ta, ma
; CHECK-NEXT:    vfrsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 4 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <vscale x 4 x bfloat> %head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer
  %vc = fsub <vscale x 4 x bfloat> %splat, %va
  ret <vscale x 4 x bfloat> %vc
}

define <vscale x 8 x bfloat> @vrsub_vf_nxv8bf16(<vscale x 8 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vrsub_vf_nxv8bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16alt, m2, ta, ma
; CHECK-NEXT:    vfrsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 8 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <vscale x 8 x bfloat> %head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
  %vc = fsub <vscale x 8 x bfloat> %splat, %va
  ret <vscale x 8 x bfloat> %vc
}

define <vscale x 16 x bfloat> @vrsub_vf_nxv16bf16(<vscale x 16 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vrsub_vf_nxv16bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16alt, m4, ta, ma
; CHECK-NEXT:    vfrsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 16 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <vscale x 16 x bfloat> %head, <vscale x 16 x bfloat> poison, <vscale x 16 x i32> zeroinitializer
  %vc = fsub <vscale x 16 x bfloat> %splat, %va
  ret <vscale x 16 x bfloat> %vc
}

define <vscale x 32 x bfloat> @vrsub_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfloat %b) {
; CHECK-LABEL: vrsub_vf_nxv32bf16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16alt, m8, ta, ma
; CHECK-NEXT:    vfrsub.vf v8, v8, fa0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 32 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <vscale x 32 x bfloat> %head, <vscale x 32 x bfloat> poison, <vscale x 32 x i32> zeroinitializer
  %vc = fsub <vscale x 32 x bfloat> %splat, %va
  ret <vscale x 32 x bfloat> %vc
}