llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-salu-float.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=OLD_RBS_GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefix=OLD_RBS_GFX12 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -new-reg-bank-select < %s | FileCheck -check-prefix=NEW_RBS_GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -new-reg-bank-select < %s | FileCheck -check-prefix=NEW_RBS_GFX12 %s

define amdgpu_ps void @salu_float(float inreg %a, float inreg %b, i32 inreg %c, ptr addrspace(1) %ptr) {
; OLD_RBS_GFX10-LABEL: salu_float:
; OLD_RBS_GFX10:       ; %bb.0:
; OLD_RBS_GFX10-NEXT:    v_add_f32_e64 v2, s0, s1
; OLD_RBS_GFX10-NEXT:    v_cvt_u32_f32_e32 v2, v2
; OLD_RBS_GFX10-NEXT:    v_add_nc_u32_e32 v2, s2, v2
; OLD_RBS_GFX10-NEXT:    global_store_dword v[0:1], v2, off
; OLD_RBS_GFX10-NEXT:    s_endpgm
;
; OLD_RBS_GFX12-LABEL: salu_float:
; OLD_RBS_GFX12:       ; %bb.0:
; OLD_RBS_GFX12-NEXT:    s_add_f32 s0, s0, s1
; OLD_RBS_GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; OLD_RBS_GFX12-NEXT:    s_cvt_u32_f32 s0, s0
; OLD_RBS_GFX12-NEXT:    s_add_co_i32 s0, s0, s2
; OLD_RBS_GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; OLD_RBS_GFX12-NEXT:    v_mov_b32_e32 v2, s0
; OLD_RBS_GFX12-NEXT:    global_store_b32 v[0:1], v2, off
; OLD_RBS_GFX12-NEXT:    s_endpgm
;
; NEW_RBS_GFX10-LABEL: salu_float:
; NEW_RBS_GFX10:       ; %bb.0:
; NEW_RBS_GFX10-NEXT:    v_add_f32_e64 v2, s0, s1
; NEW_RBS_GFX10-NEXT:    v_cvt_u32_f32_e32 v2, v2
; NEW_RBS_GFX10-NEXT:    v_readfirstlane_b32 s0, v2
; NEW_RBS_GFX10-NEXT:    s_add_i32 s0, s0, s2
; NEW_RBS_GFX10-NEXT:    v_mov_b32_e32 v2, s0
; NEW_RBS_GFX10-NEXT:    global_store_dword v[0:1], v2, off
; NEW_RBS_GFX10-NEXT:    s_endpgm
;
; NEW_RBS_GFX12-LABEL: salu_float:
; NEW_RBS_GFX12:       ; %bb.0:
; NEW_RBS_GFX12-NEXT:    s_add_f32 s0, s0, s1
; NEW_RBS_GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; NEW_RBS_GFX12-NEXT:    s_cvt_u32_f32 s0, s0
; NEW_RBS_GFX12-NEXT:    s_add_co_i32 s0, s0, s2
; NEW_RBS_GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; NEW_RBS_GFX12-NEXT:    v_mov_b32_e32 v2, s0
; NEW_RBS_GFX12-NEXT:    global_store_b32 v[0:1], v2, off
; NEW_RBS_GFX12-NEXT:    s_endpgm
  %add = fadd float %a, %b
  %add.i32 = fptoui float %add to i32
  %res = add i32 %add.i32, %c
  store i32 %res, ptr addrspace(1) %ptr
  ret void
}