llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-amount-zext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s

---
name:            lshr_zext_i16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: lshr_zext_i16
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
    ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
    ; CHECK-NEXT: %res:sgpr(s32) = G_LSHR %src, [[AND]](s32)
    ; CHECK-NEXT: $sgpr0 = COPY %res(s32)
    %src:sgpr(s32) = COPY $sgpr0
    %regamt:sgpr(s32) = COPY $sgpr1
    %amt:sgpr(s16) = G_TRUNC %regamt
    %zextamt:sgpr(s32) = G_ZEXT %amt
    %res:sgpr(s32) = G_LSHR %src, %zextamt
    $sgpr0 = COPY %res
...

---
name:            ashr_zext_i16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: ashr_zext_i16
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
    ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
    ; CHECK-NEXT: %res:sgpr(s32) = G_ASHR %src, [[AND]](s32)
    ; CHECK-NEXT: $sgpr0 = COPY %res(s32)
    %src:sgpr(s32) = COPY $sgpr0
    %regamt:sgpr(s32) = COPY $sgpr1
    %amt:sgpr(s16) = G_TRUNC %regamt
    %zextamt:sgpr(s32) = G_ZEXT %amt
    %res:sgpr(s32) = G_ASHR %src, %zextamt
    $sgpr0 = COPY %res
...

---
name:            shl_zext_i16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: shl_zext_i16
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
    ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
    ; CHECK-NEXT: %res:sgpr(s32) = G_SHL %src, [[AND]](s32)
    ; CHECK-NEXT: $sgpr0 = COPY %res(s32)
    %src:sgpr(s32) = COPY $sgpr0
    %regamt:sgpr(s32) = COPY $sgpr1
    %amt:sgpr(s16) = G_TRUNC %regamt
    %zextamt:sgpr(s32) = G_ZEXT %amt
    %res:sgpr(s32) = G_SHL %src, %zextamt
    $sgpr0 = COPY %res
...

---
name:            lshr_zext_i8
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: lshr_zext_i8
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
    ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
    ; CHECK-NEXT: %res:sgpr(s32) = G_LSHR %src, [[AND]](s32)
    ; CHECK-NEXT: $sgpr0 = COPY %res(s32)
    %src:sgpr(s32) = COPY $sgpr0
    %regamt:sgpr(s32) = COPY $sgpr1
    %amt:sgpr(s8) = G_TRUNC %regamt
    %zextamt:sgpr(s32) = G_ZEXT %amt
    %res:sgpr(s32) = G_LSHR %src, %zextamt
    $sgpr0 = COPY %res
...

---
name:            ashr_zext_i8
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: ashr_zext_i8
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
    ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
    ; CHECK-NEXT: %res:sgpr(s32) = G_ASHR %src, [[AND]](s32)
    ; CHECK-NEXT: $sgpr0 = COPY %res(s32)
    %src:sgpr(s32) = COPY $sgpr0
    %regamt:sgpr(s32) = COPY $sgpr1
    %amt:sgpr(s8) = G_TRUNC %regamt
    %zextamt:sgpr(s32) = G_ZEXT %amt
    %res:sgpr(s32) = G_ASHR %src, %zextamt
    $sgpr0 = COPY %res
...

---
name:            shl_zext_i8
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; CHECK-LABEL: name: shl_zext_i8
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %src:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: %regamt:sgpr(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
    ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND %regamt, [[C]]
    ; CHECK-NEXT: %res:sgpr(s32) = G_SHL %src, [[AND]](s32)
    ; CHECK-NEXT: $sgpr0 = COPY %res(s32)
    %src:sgpr(s32) = COPY $sgpr0
    %regamt:sgpr(s32) = COPY $sgpr1
    %amt:sgpr(s8) = G_TRUNC %regamt
    %zextamt:sgpr(s32) = G_ZEXT %amt
    %res:sgpr(s32) = G_SHL %src, %zextamt
    $sgpr0 = COPY %res
...