llvm/test/CodeGen/AArch64/arm64-cvt-simd-round-rint-strictfp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFPRCVT

;
; Lround strictfp
;

define float @lround_i32_f16_simd_exp(half %x)  {
; CHECK-FPRCVT-LABEL: lround_i32_f16_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    fcvtas s0, h0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: lround_i32_f16_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.lround.i32.f16(half %x, metadata !"fpexcept.strict")
  %sum = bitcast i32 %val to float
  ret float %sum
}

define float @lround_i32_f32_simd_exp(float %x)  {
; CHECK-LABEL: lround_i32_f32_simd_exp:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas s0, s0
; CHECK-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.lround.i32.f32(float %x, metadata !"fpexcept.strict")
  %bc  = bitcast i32 %val to float
  ret float %bc
}

define float @lround_i32_f64_simd_exp(double %x)  {
; CHECK-FPRCVT-LABEL: lround_i32_f64_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    fcvtas s0, d0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: lround_i32_f64_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.lround.i32.f64(double %x, metadata !"fpexcept.strict")
  %bc  = bitcast i32 %val to float
  ret float %bc
}

define double @lround_i64_f16_simd_exp(half %x)  {
; CHECK-FPRCVT-LABEL: lround_i64_f16_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    fcvtas d0, h0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: lround_i64_f16_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.lround.i64.f16(half %x, metadata !"fpexcept.strict")
  %bc  = bitcast i64 %val to double
  ret double %bc
}

define double @lround_i64_f32_simd_exp(float %x)  {
; CHECK-FPRCVT-LABEL: lround_i64_f32_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    fcvtas d0, s0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: lround_i64_f32_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.lround.i64.f32(float %x, metadata !"fpexcept.strict")
  %bc  = bitcast i64 %val to double
  ret double %bc
}

define double @lround_i64_f64_simd_exp(double %x)  {
; CHECK-LABEL: lround_i64_f64_simd_exp:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas d0, d0
; CHECK-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.lround.i64.f64(double %x, metadata !"fpexcept.strict")
  %bc  = bitcast i64 %val to double
  ret double %bc
}

;
; Llround strictfp
;

define double @llround_i64_f16_simd_exp(half %x)  {
; CHECK-FPRCVT-LABEL: llround_i64_f16_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    fcvtas d0, h0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: llround_i64_f16_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.llround.i64.f16(half %x, metadata !"fpexcept.strict")
  %sum = bitcast i64 %val to double
  ret double %sum
}

define double @llround_i64_f32_simd_exp(float %x)  {
; CHECK-FPRCVT-LABEL: llround_i64_f32_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    fcvtas d0, s0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: llround_i64_f32_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.llround.i64.f32(float %x, metadata !"fpexcept.strict")
  %bc  = bitcast i64 %val to double
  ret double %bc
}

define double @llround_i64_f64_simd_exp(double %x)  {
; CHECK-LABEL: llround_i64_f64_simd_exp:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas d0, d0
; CHECK-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.llround.i64.f64(double %x, metadata !"fpexcept.strict")
  %bc  = bitcast i64 %val to double
  ret double %bc
}

;
; Lrint strictfp
;

define float @lrint_i32_f16_simd_exp(half %x)  {
; CHECK-FPRCVT-LABEL: lrint_i32_f16_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    frintx h0, h0
; CHECK-FPRCVT-NEXT:    fcvtzs s0, h0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: lrint_i32_f16_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    frintx h0, h0
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.lrint.i32.f16(half %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
  %sum = bitcast i32 %val to float
  ret float %sum
}

define float @lrint_i32_f32_simd_exp(float %x)  {
; CHECK-LABEL: lrint_i32_f32_simd_exp:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx s0, s0
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.lrint.i32.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
  %bc  = bitcast i32 %val to float
  ret float %bc
}

define float @lrint_i32_f64_simd_exp(double %x)  {
; CHECK-FPRCVT-LABEL: lrint_i32_f64_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    frintx d0, d0
; CHECK-FPRCVT-NEXT:    fcvtzs s0, d0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: lrint_i32_f64_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    frintx d0, d0
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.lrint.i32.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
  %bc  = bitcast i32 %val to float
  ret float %bc
}

define double @lrint_i64_f16_simd_exp(half %x)  {
; CHECK-FPRCVT-LABEL: lrint_i64_f16_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    frintx h0, h0
; CHECK-FPRCVT-NEXT:    fcvtzs d0, h0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: lrint_i64_f16_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    frintx h0, h0
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.lrint.i53.f16(half %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
  %bc  = bitcast i64 %val to double
  ret double %bc
}

define double @lrint_i64_f32_simd_exp(float %x)  {
; CHECK-FPRCVT-LABEL: lrint_i64_f32_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    frintx s0, s0
; CHECK-FPRCVT-NEXT:    fcvtzs d0, s0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: lrint_i64_f32_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    frintx s0, s0
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.lrint.i64.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
  %bc  = bitcast i64 %val to double
  ret double %bc
}

define double @lrint_i64_f64_simd_exp(double %x)  {
; CHECK-LABEL: lrint_i64_f64_simd_exp:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx d0, d0
; CHECK-NEXT:    fcvtzs d0, d0
; CHECK-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.lrint.i64.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
  %bc  = bitcast i64 %val to double
  ret double %bc
}

;
; Llrint strictfp
;

define double @llrint_i64_f16_simd_exp(half %x)  {
; CHECK-FPRCVT-LABEL: llrint_i64_f16_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    frintx h0, h0
; CHECK-FPRCVT-NEXT:    fcvtzs d0, h0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: llrint_i64_f16_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    frintx h0, h0
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.llrint.i64.f16(half %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
  %sum = bitcast i64 %val to double
  ret double %sum
}

define double @llrint_i64_f32_simd_exp(float %x)  {
; CHECK-FPRCVT-LABEL: llrint_i64_f32_simd_exp:
; CHECK-FPRCVT:       // %bb.0:
; CHECK-FPRCVT-NEXT:    frintx s0, s0
; CHECK-FPRCVT-NEXT:    fcvtzs d0, s0
; CHECK-FPRCVT-NEXT:    ret
;
; CHECK-NOFPRCVT-LABEL: llrint_i64_f32_simd_exp:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    frintx s0, s0
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.llrint.i64.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
  %bc  = bitcast i64 %val to double
  ret double %bc
}

define double @llrint_i64_f64_simd_exp(double %x)  {
; CHECK-LABEL: llrint_i64_f64_simd_exp:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx d0, d0
; CHECK-NEXT:    fcvtzs d0, d0
; CHECK-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.llrint.i64.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
  %bc  = bitcast i64 %val to double
  ret double %bc
}