llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extendedLLTs.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgpu12.51 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o - 2> %t | FileCheck -check-prefix=GCN %s

# G_ADD i32: -> tablegen S_ADD_I32;
# G_ADD s32: -> manual S_ADD_U32; selectG_ADD_SUB

---
name: g_add_op0_sgpr_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; GCN-LABEL: name: g_add_op0_sgpr_i32
    ; GCN: liveins: $sgpr0, $sgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GCN-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]]
    %0:sgpr(i32) = COPY $sgpr0
    %1:sgpr(i32) = COPY $sgpr1
    %2:sgpr(i32) = G_ADD %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_add_op0_sgpr_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; GCN-LABEL: name: g_add_op0_sgpr_s32
    ; GCN: liveins: $sgpr0, $sgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GCN-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def dead $scc
    ; GCN-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s32) = G_ADD %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_fcmp_op2_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_fcmp_op2_f32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
    %0:vgpr(f32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_fcmp_op2_fconstant_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_fcmp_op2_fconstant_f32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[V_MOV_B32_e32_]], 0, [[COPY]], 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
    %0:vgpr(f32) = G_FCONSTANT float 1.0
    %1:vgpr(s32) = COPY $vgpr0
    %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_fcmp_op3_fconstant_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_fcmp_op3_fconstant_s32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
    ; GCN-NEXT: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[V_MOV_B32_e32_]], 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
    %0:vgpr(f32) = COPY $vgpr0
    %1:vgpr(s32) = G_FCONSTANT float 1.0
    %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_shl_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_shl_op0_i32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(i32) = G_SHL %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_fpext_op0_f64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_fpext_op0_f64
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_CVT_F64_F32_e64_:%[0-9]+]]:vreg_64_align2 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_F64_F32_e64_]]
    %0:vgpr(f32) = COPY $vgpr0
    %1:vgpr(f64) = G_FPEXT %0
    S_ENDPGM 0, implicit %1
...

---
name: g_lshr_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_lshr_op0_i32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(i32) = G_LSHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_ashr_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_ashr_op0_i32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(i32) = G_ASHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_fptrunc_op0_f16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_fptrunc_op0_f16
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_F16_F32_t16_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(f16) = G_FPTRUNC %0
    S_ENDPGM 0, implicit %1
...

---
name: g_zextload_op0_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_zextload_op0_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[DS_READ_U8_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_U8_gfx9 [[COPY]], 0, 0, implicit $exec :: (load (s8), addrspace 3)
    ; GCN-NEXT: $vgpr0 = COPY [[DS_READ_U8_gfx9_]]
    %0:vgpr(p3) = COPY $vgpr0
    %1:vgpr(i32) = G_ZEXTLOAD %0 :: (load (s8), align 1, addrspace 3)
    $vgpr0 = COPY %1
...

---
name: g_sextload_op0_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_sextload_op0_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[DS_READ_I8_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_I8_gfx9 [[COPY]], 0, 0, implicit $exec :: (load (s8), addrspace 3)
    ; GCN-NEXT: $vgpr0 = COPY [[DS_READ_I8_gfx9_]]
    %0:vgpr(p3) = COPY $vgpr0
    %1:vgpr(i32) = G_SEXTLOAD %0 :: (load (s8), align 1, addrspace 3)
    $vgpr0 = COPY %1
...

---
name: g_umin_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_umin_op0_i32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(i32) = G_UMIN %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_umin_op0_i64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; GCN-LABEL: name: g_umin_op0_i64
    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
    ; GCN-NEXT: [[V_MIN_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_U64_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U64_e64_]]
    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %2:vgpr(i64) = G_UMIN %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_umax_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_umax_op0_i32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_U32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(i32) = G_UMAX %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_uitofp_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_uitofp_op0_f32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
    %0:vgpr(i32) = COPY $vgpr0
    %1:vgpr(f32) = G_UITOFP %0
    $vgpr0 = COPY %1
...

---
name: g_umax_op0_i64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; GCN-LABEL: name: g_umax_op0_i64
    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
    ; GCN-NEXT: [[V_MAX_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MAX_U64_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_U64_e64_]]
    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %2:vgpr(i64) = G_UMAX %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_smin_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_smin_op0_i32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_I32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(i32) = G_SMIN %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_smax_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_smax_op0_i32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_I32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(i32) = G_SMAX %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_fma_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2
    ; GCN-LABEL: name: g_fma_op0_f32
    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN-NEXT: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: $vgpr0 = COPY [[V_FMAC_F32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr2
    %3:vgpr(f32) = G_FMA %0, %1, %2
    $vgpr0 = COPY %3
...

---
name: g_uitofp_op1_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_uitofp_op1_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
    %0:vgpr(i32) = COPY $vgpr0
    %1:vgpr(f32) = G_UITOFP %0
    $vgpr0 = COPY %1
...

---
name: g_fmaxnum_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_fmaxnum_op0_f32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: $vgpr0 = COPY [[V_MAX_F32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(f32) = G_FMAXNUM %0, %1
    $vgpr0 = COPY %2
...

---
name: g_fminnum_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_fminnum_op0_f32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: $vgpr0 = COPY [[V_MIN_F32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(f32) = G_FMINNUM %0, %1
    $vgpr0 = COPY %2
...

---
name: g_fmaxnum_ieee_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_fmaxnum_ieee_op0_f32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: $vgpr0 = COPY [[V_MAX_F32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(f32) = G_FMAXNUM_IEEE %0, %1
    $vgpr0 = COPY %2
...

---
name: g_fminnum_ieee_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_fminnum_ieee_op0_f32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: $vgpr0 = COPY [[V_MIN_F32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(f32) = G_FMINNUM_IEEE %0, %1
    $vgpr0 = COPY %2
...

---
name: g_intrinsic_amdgcn_class_op2_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_intrinsic_amdgcn_class_op2_f32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
    %0:vgpr(f32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_intrinsic_convergent_amdgcn_readfirstlane_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_intrinsic_convergent_amdgcn_readfirstlane_op0_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_READFIRSTLANE_B32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %0
    S_ENDPGM 0, implicit %1
...

---
name: g_amdgpu_atomic_cmpxchg_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; GCN-LABEL: name: g_amdgpu_atomic_cmpxchg_op0_i32
    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
    ; GCN-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:vgpr(i32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
    ; GCN-NEXT: S_ENDPGM 0, implicit [[AMDGPU_ATOMIC_CMPXCHG]](i32)
    %0:vgpr(p1) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %2:vgpr(i32) = G_AMDGPU_ATOMIC_CMPXCHG %0, %1 :: (load store seq_cst (s32), addrspace 1)
    S_ENDPGM 0, implicit %2
...

---
name: g_amdgpu_ffbh_u32_op1_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_amdgpu_ffbh_u32_op1_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
    %0:vgpr(i32) = COPY $vgpr0
    %1:vgpr(s32) = G_AMDGPU_FFBH_U32 %0
    S_ENDPGM 0, implicit %1
...

---
name: g_amdgpu_ffbl_b32_op1_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_amdgpu_ffbl_b32_op1_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
    %0:vgpr(i32) = COPY $vgpr0
    %1:vgpr(s32) = G_AMDGPU_FFBL_B32 %0
    S_ENDPGM 0, implicit %1
...

---
name: g_bitreverse_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_bitreverse_op0_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(i32) = G_BITREVERSE %0
    S_ENDPGM 0, implicit %1
...

---
name: g_ctlz_zero_poison_op1_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_ctlz_zero_poison_op1_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]
    %0:vgpr(i32) = COPY $vgpr0
    %1:vgpr(s32) = G_CTLZ_ZERO_POISON %0
    S_ENDPGM 0, implicit %1
...

---
name: g_ctpop_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_ctpop_op0_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], 0, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]]
    %0:vgpr(i32) = COPY $vgpr0
    %1:vgpr(i32) = G_CTPOP %0
    S_ENDPGM 0, implicit %1
...

---
name: g_cttz_zero_poison_op1_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_cttz_zero_poison_op1_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_FFBL_B32_e64_:%[0-9]+]]:vgpr_32 = V_FFBL_B32_e64 [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_FFBL_B32_e64_]]
    %0:vgpr(i32) = COPY $vgpr0
    %1:vgpr(s32) = G_CTTZ_ZERO_POISON %0
    S_ENDPGM 0, implicit %1
...

---
name: g_fadd_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_fadd_op0_f32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(f32) = G_FADD %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_fcanonicalize_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_fcanonicalize_op0_f32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MAX_F32_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(f32) = G_FCANONICALIZE %0
    S_ENDPGM 0, implicit %1
...

---
name: g_fneg_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_fneg_op0_f32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
    ; GCN-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(f32) = G_FNEG %0
    S_ENDPGM 0, implicit %1
...

---
name: g_ffloor_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_ffloor_op0_f32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_FLOOR_F32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(f32) = G_FFLOOR %0
    S_ENDPGM 0, implicit %1
...

---
name: g_fexp2_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_fexp2_op0_f32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; GCN-NEXT: [[FEXP2_:%[0-9]+]]:vgpr(f32) = G_FEXP2 [[COPY]]
    ; GCN-NEXT: S_ENDPGM 0, implicit [[FEXP2_]](f32)
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(f32) = G_FEXP2 %0
    S_ENDPGM 0, implicit %1
...



---
name: g_fmul_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: g_fmul_op0_f32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MUL_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(f32) = G_FMUL %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: g_fabs_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_fabs_op0_f32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
    ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(f32) = G_FABS %0
    S_ENDPGM 0, implicit %1
...

---
name: g_fptosi_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_fptosi_op0_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_I32_F32_e64_]]
    %0:vgpr(f32) = COPY $vgpr0
    %1:vgpr(i32) = G_FPTOSI %0
    S_ENDPGM 0, implicit %1
...

---
name: g_fptoui_op0_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_fptoui_op0_i32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_U32_F32_e64_]]
    %0:vgpr(f32) = COPY $vgpr0
    %1:vgpr(i32) = G_FPTOUI %0
    S_ENDPGM 0, implicit %1
...

---
name: g_fshr_op3_i32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2
    ; GCN-LABEL: name: g_fshr_op3_i32
    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY2]].lo16
    ; GCN-NEXT: [[V_ALIGNBIT_B32_t16_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_t16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY3]], 0, 0, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_t16_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(i32) = COPY $vgpr2
    %3:vgpr(s32) = G_FSHR %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: g_intrinsic_trunc_op0_f32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0
    ; GCN-LABEL: name: g_intrinsic_trunc_op0_f32
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_TRUNC_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_TRUNC_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
    ; GCN-NEXT: S_ENDPGM 0, implicit [[V_TRUNC_F32_e64_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(f32) = G_INTRINSIC_TRUNC %0
    S_ENDPGM 0, implicit %1
...