blob: c588b768d83329f86eb2edfefae9d6b5301eb1e7 [file] [edit]
//===- llvm/unittest/CodeGen/AMDGPUMetadataTest.cpp -----------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
/// \file
/// Test that MFMA co-exec rules are defined for all gfx950 MFMA instructions.
//
//===----------------------------------------------------------------------===//
#include "AMDGPUUnitTests.h"
#include "gtest/gtest.h"
#include "AMDGPUCoExecInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include "GCNSubtarget.h"
#include "SIInstrInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#define GET_AVAILABLE_OPCODE_CHECKER
#include "AMDGPUGenInstrInfo.inc"
using namespace llvm;
using namespace llvm::AMDGPU;
class AMDGPUMFMACoExecRules : public AMDGPUTestBase {};
TEST_F(AMDGPUMFMACoExecRules, GFX950) {
std::unique_ptr<GCNTargetMachine> TM =
createAMDGPUTargetMachine(Triple("amdgpu-amd-amdhsa"), "gfx950", "");
auto ST =
std::make_unique<GCNSubtarget>(TM->getTargetTriple(), TM->getTargetCPU(),
TM->getTargetFeatureString(), *TM);
const MCInstrInfo *MCII = TM->getMCInstrInfo();
for (unsigned Op = 0; Op < MCII->getNumOpcodes(); ++Op) {
if (!ST->getInstrInfo()->isMFMAorWMMA(Op))
continue;
// Filter out pre-gfx950 MFMA instructions
FeatureBitset Required = AMDGPU_MC::computeRequiredFeatures(Op);
if (!Required.test(AMDGPU_MC::Feature_HasGFX950InstsBit))
continue;
CoExecInfo Info = getMFMACoExecInfo(Op);
// None of gfx950 MFMAs can co-execute anything in their issue slot and our
// fallback for unrecognized MFMA instructions is to allow everything in
// every slot, so here we check that we did not encounter the fallback
// definition of co-exec rules.
EXPECT_EQ(Info.Slots[0].Mask, CoExecMask::None) << MCII->getName(Op);
}
}