llvm/test/CodeGen/X86/pr166744.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=POSTRA
; RUN: llc < %s -mtriple=x86_64-- -mcpu=haswell | FileCheck %s --check-prefixes=NOPOSTRA
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=NOPOSTRA

; Ensure reloads are after narrowed i512 -> i32 store
define i1 @PR166744(ptr %v, i64 %idx, i1 zeroext %b) {
; POSTRA-LABEL: PR166744:
; POSTRA:       # %bb.0:
; POSTRA-NEXT:    movl $1029, %eax # imm = 0x405
; POSTRA-NEXT:    shlxl %esi, %edx, %edx
; POSTRA-NEXT:    bextrl %eax, %esi, %eax
; POSTRA-NEXT:    movl (%rdi,%rax,4), %ecx
; POSTRA-NEXT:    btrl %esi, %ecx
; POSTRA-NEXT:    orl %ecx, %edx
; POSTRA-NEXT:    movl %edx, (%rdi,%rax,4)
; POSTRA-NEXT:    vmovdqu (%rdi), %ymm0
; POSTRA-NEXT:    vpor 32(%rdi), %ymm0, %ymm0
; POSTRA-NEXT:    vptest %ymm0, %ymm0
; POSTRA-NEXT:    setne %al
; POSTRA-NEXT:    vzeroupper
; POSTRA-NEXT:    retq
;
; NOPOSTRA-LABEL: PR166744:
; NOPOSTRA:       # %bb.0:
; NOPOSTRA-NEXT:    movl %esi, %eax
; NOPOSTRA-NEXT:    shrl $3, %esi
; NOPOSTRA-NEXT:    andl $60, %esi
; NOPOSTRA-NEXT:    movl (%rdi,%rsi), %ecx
; NOPOSTRA-NEXT:    btrl %eax, %ecx
; NOPOSTRA-NEXT:    shlxl %eax, %edx, %eax
; NOPOSTRA-NEXT:    orl %ecx, %eax
; NOPOSTRA-NEXT:    movl %eax, (%rdi,%rsi)
; NOPOSTRA-NEXT:    vmovdqu (%rdi), %ymm0
; NOPOSTRA-NEXT:    vpor 32(%rdi), %ymm0, %ymm0
; NOPOSTRA-NEXT:    vptest %ymm0, %ymm0
; NOPOSTRA-NEXT:    setne %al
; NOPOSTRA-NEXT:    vzeroupper
; NOPOSTRA-NEXT:    retq
  %rem = and i64 %idx, 511
  %sh_prom = zext nneg i64 %rem to i512
  %shl = shl nuw i512 1, %sh_prom
  %not = xor i512 %shl, -1
  %load = load i512, ptr %v, align 8
  %and = and i512 %load, %not
  %conv2 = zext i1 %b to i512
  %shl4 = shl nuw i512 %conv2, %sh_prom
  %or = or i512 %and, %shl4
  store i512 %or, ptr %v, align 8
  %cmp = icmp ne i512 %or, 0
  ret i1 %cmp
}