llvm/test/CodeGen/RISCV/xqcibm-regalloc-hints.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV32ZBS
; RUN: llc -mtriple=riscv32 -mattr=+zbs,+xqcibm -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV32ZBSXQCIBM

define signext i32 @bexti_hints(i32 %a, i32 signext %b, i32 %c) nounwind {
; RV32I-LABEL: bexti_hints:
; RV32I:       # %bb.0:
; RV32I-NEXT:    slli a1, a1, 26
; RV32I-NEXT:    srli a1, a1, 31
; RV32I-NEXT:    addi a0, a1, 2047
; RV32I-NEXT:    addi a0, a0, 1286
; RV32I-NEXT:    ret
;
; RV32ZBS-LABEL: bexti_hints:
; RV32ZBS:       # %bb.0:
; RV32ZBS-NEXT:    bexti a0, a1, 5
; RV32ZBS-NEXT:    addi a0, a0, 2047
; RV32ZBS-NEXT:    addi a0, a0, 1286
; RV32ZBS-NEXT:    ret
;
; RV32ZBSXQCIBM-LABEL: bexti_hints:
; RV32ZBSXQCIBM:       # %bb.0:
; RV32ZBSXQCIBM-NEXT:    bexti a1, a1, 5
; RV32ZBSXQCIBM-NEXT:    addi a0, a1, 2047
; RV32ZBSXQCIBM-NEXT:    addi a0, a0, 1286
; RV32ZBSXQCIBM-NEXT:    ret
  %and = and i32 %b, 32
  %cmp = icmp ne i32 %and, 0
  %zext = zext i1 %cmp to i32
  %add = add i32 %zext, 3333
  ret i32 %add
}

define i32 @bseti_hints(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: bseti_hints:
; RV32I:       # %bb.0:
; RV32I-NEXT:    li a0, 1
; RV32I-NEXT:    slli a0, a0, 11
; RV32I-NEXT:    or a1, a1, a0
; RV32I-NEXT:    add a0, a1, a0
; RV32I-NEXT:    addi a0, a0, 1285
; RV32I-NEXT:    ret
;
; RV32ZBS-LABEL: bseti_hints:
; RV32ZBS:       # %bb.0:
; RV32ZBS-NEXT:    bseti a0, a1, 11
; RV32ZBS-NEXT:    addi a0, a0, 2047
; RV32ZBS-NEXT:    addi a0, a0, 1286
; RV32ZBS-NEXT:    ret
;
; RV32ZBSXQCIBM-LABEL: bseti_hints:
; RV32ZBSXQCIBM:       # %bb.0:
; RV32ZBSXQCIBM-NEXT:    bseti a1, a1, 11
; RV32ZBSXQCIBM-NEXT:    addi a0, a1, 2047
; RV32ZBSXQCIBM-NEXT:    addi a0, a0, 1286
; RV32ZBSXQCIBM-NEXT:    ret
  %or = or i32 %b, 2048
  %add = add i32 %or, 3333
  ret i32 %add
}