llvm/test/CodeGen/RISCV/rvp-widening-convert.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; This file covers packed widening conversions from the generic IR generated by
; the C intrinsic header.
; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+m,+zbb \
; RUN:   -verify-machineinstrs < %s | \
; RUN:   FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb \
; RUN:   -verify-machineinstrs < %s | \
; RUN:   FileCheck %s --check-prefixes=CHECK,RV64

define <4 x i16> @test_pwcvt_v4i8(<4 x i8> %a) {
; RV32-LABEL: test_pwcvt_v4i8:
; RV32:       # %bb.0:
; RV32-NEXT:    pwcvt.b a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test_pwcvt_v4i8:
; RV64:       # %bb.0:
; RV64-NEXT:    pwcvtu.wb a0, a0
; RV64-NEXT:    psext.h.b a0, a0
; RV64-NEXT:    ret
  %res = sext <4 x i8> %a to <4 x i16>
  ret <4 x i16> %res
}

define <2 x i32> @test_pwcvt_v2i16(<2 x i16> %a) {
; RV32-LABEL: test_pwcvt_v2i16:
; RV32:       # %bb.0:
; RV32-NEXT:    pwcvt.h a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test_pwcvt_v2i16:
; RV64:       # %bb.0:
; RV64-NEXT:    pwcvtu.wh a0, a0
; RV64-NEXT:    psext.w.h a0, a0
; RV64-NEXT:    ret
  %res = sext <2 x i16> %a to <2 x i32>
  ret <2 x i32> %res
}

define <4 x i16> @test_pwcvtu_v4i8(<4 x i8> %a) {
; RV32-LABEL: test_pwcvtu_v4i8:
; RV32:       # %bb.0:
; RV32-NEXT:    pwcvtu.b a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test_pwcvtu_v4i8:
; RV64:       # %bb.0:
; RV64-NEXT:    pwcvtu.wb a0, a0
; RV64-NEXT:    ret
  %res = zext <4 x i8> %a to <4 x i16>
  ret <4 x i16> %res
}

define <2 x i32> @test_pwcvtu_v2i16(<2 x i16> %a) {
; RV32-LABEL: test_pwcvtu_v2i16:
; RV32:       # %bb.0:
; RV32-NEXT:    pwcvtu.h a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test_pwcvtu_v2i16:
; RV64:       # %bb.0:
; RV64-NEXT:    pwcvtu.wh a0, a0
; RV64-NEXT:    ret
  %res = zext <2 x i16> %a to <2 x i32>
  ret <2 x i32> %res
}

define <4 x i16> @test_pwcvth_v4i8(<4 x i8> %a) {
; RV32-LABEL: test_pwcvth_v4i8:
; RV32:       # %bb.0:
; RV32-NEXT:    pwcvth.b a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test_pwcvth_v4i8:
; RV64:       # %bb.0:
; RV64-NEXT:    pwcvth.wb a0, a0
; RV64-NEXT:    ret
  %shuffle = shufflevector <4 x i8> zeroinitializer, <4 x i8> %a, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
  %res = bitcast <8 x i8> %shuffle to <4 x i16>
  ret <4 x i16> %res
}

define <2 x i32> @test_pwcvth_v2i16(<2 x i16> %a) {
; RV32-LABEL: test_pwcvth_v2i16:
; RV32:       # %bb.0:
; RV32-NEXT:    pwcvth.h a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test_pwcvth_v2i16:
; RV64:       # %bb.0:
; RV64-NEXT:    pwcvth.wh a0, a0
; RV64-NEXT:    ret
  %shuffle = shufflevector <2 x i16> zeroinitializer, <2 x i16> %a, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
  %res = bitcast <4 x i16> %shuffle to <2 x i32>
  ret <2 x i32> %res
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}