| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+zbb -verify-machineinstrs \ |
| ; RUN: < %s | FileCheck %s |
| |
| define i32 @abs_i32(i32 %x) { |
| ; CHECK-LABEL: abs_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: absw a0, a0 |
| ; CHECK-NEXT: ret |
| %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) |
| ret i32 %abs |
| } |
| |
| define signext i32 @abs_i32_sext(i32 signext %x) { |
| ; CHECK-LABEL: abs_i32_sext: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: absw a0, a0 |
| ; CHECK-NEXT: ret |
| %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) |
| ret i32 %abs |
| } |
| |
| define i64 @abs_i64(i64 %x) { |
| ; CHECK-LABEL: abs_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: abs a0, a0 |
| ; CHECK-NEXT: ret |
| %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) |
| ret i64 %abs |
| } |
| |
| define i64 @pack_i64_imm() { |
| ; CHECK-LABEL: pack_i64_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lui a0, 16432 |
| ; CHECK-NEXT: addi a0, a0, 513 |
| ; CHECK-NEXT: pack a0, a0, a0 |
| ; CHECK-NEXT: ret |
| ret i64 u0x0403020104030201 |
| } |
| |
| ; Make sure we prefer li over pli |
| define i64 @li_imm() { |
| ; CHECK-LABEL: li_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: li a0, -1 |
| ; CHECK-NEXT: ret |
| ret i64 -1 |
| } |
| |
| define i32 @pli_b_i32() { |
| ; CHECK-LABEL: pli_b_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lui a0, 20560 |
| ; CHECK-NEXT: addi a0, a0, 1285 |
| ; CHECK-NEXT: ret |
| ret i32 u0x05050505 |
| } |
| |
| define i64 @pli_b_i64() { |
| ; CHECK-LABEL: pli_b_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pli.b a0, -128 |
| ; CHECK-NEXT: ret |
| ret i64 u0x8080808080808080 |
| } |
| |
| define i32 @pli_h_i32() { |
| ; CHECK-LABEL: pli_h_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lui a0, 1047840 |
| ; CHECK-NEXT: addi a0, a0, -47 |
| ; CHECK-NEXT: ret |
| ret i32 u0xffd1ffd1 |
| } |
| |
| define i64 @pli_h_i64() { |
| ; CHECK-LABEL: pli_h_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pli.h a0, 291 |
| ; CHECK-NEXT: ret |
| ret i64 u0x0123012301230123 |
| } |
| |
| define i64 @pli_w_i64() { |
| ; CHECK-LABEL: pli_w_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pli.w a0, -292 |
| ; CHECK-NEXT: ret |
| ret i64 u0xfffffedcfffffedc |
| } |
| |
| define void @pli_b_store_i32(ptr %p) { |
| ; CHECK-LABEL: pli_b_store_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pli.b a1, 65 |
| ; CHECK-NEXT: sw a1, 0(a0) |
| ; CHECK-NEXT: ret |
| store i32 u0x41414141, ptr %p |
| ret void |
| } |
| |
| define i64 @pack_i64(i64 %a, i64 %b) nounwind { |
| ; CHECK-LABEL: pack_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pack a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %shl = and i64 %a, 4294967295 |
| %shl1 = shl i64 %b, 32 |
| %or = or i64 %shl1, %shl |
| ret i64 %or |
| } |
| |
| define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind { |
| ; CHECK-LABEL: pack_i64_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pack a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %zexta = zext i32 %a to i64 |
| %zextb = zext i32 %b to i64 |
| %shl1 = shl i64 %zextb, 32 |
| %or = or i64 %shl1, %zexta |
| ret i64 %or |
| } |
| |
| define i64 @pack_i64_3(ptr %0, ptr %1) { |
| ; CHECK-LABEL: pack_i64_3: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lw a0, 0(a0) |
| ; CHECK-NEXT: lw a1, 0(a1) |
| ; CHECK-NEXT: pack a0, a1, a0 |
| ; CHECK-NEXT: ret |
| %3 = load i32, ptr %0, align 4 |
| %4 = zext i32 %3 to i64 |
| %5 = shl i64 %4, 32 |
| %6 = load i32, ptr %1, align 4 |
| %7 = zext i32 %6 to i64 |
| %8 = or i64 %5, %7 |
| ret i64 %8 |
| } |
| |
| define i8 @cls_i8(i8 %x) { |
| ; CHECK-LABEL: cls_i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sext.b a0, a0 |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: addi a0, a0, -56 |
| ; CHECK-NEXT: ret |
| %a = ashr i8 %x, 7 |
| %b = xor i8 %x, %a |
| %c = call i8 @llvm.ctlz.i8(i8 %b, i1 false) |
| %d = sub i8 %c, 1 |
| ret i8 %d |
| } |
| |
| define i8 @cls_i8_2(i8 %x) { |
| ; CHECK-LABEL: cls_i8_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sext.b a0, a0 |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: addi a0, a0, -56 |
| ; CHECK-NEXT: ret |
| %a = ashr i8 %x, 7 |
| %b = xor i8 %x, %a |
| %c = shl i8 %b, 1 |
| %d = or i8 %c, 1 |
| %e = call i8 @llvm.ctlz.i8(i8 %d, i1 true) |
| ret i8 %e |
| } |
| |
| define i16 @cls_i16(i16 %x) { |
| ; CHECK-LABEL: cls_i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sext.h a0, a0 |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: addi a0, a0, -48 |
| ; CHECK-NEXT: ret |
| %a = ashr i16 %x, 15 |
| %b = xor i16 %x, %a |
| %c = call i16 @llvm.ctlz.i16(i16 %b, i1 false) |
| %d = sub i16 %c, 1 |
| ret i16 %d |
| } |
| |
| define i16 @cls_i16_2(i16 %x) { |
| ; CHECK-LABEL: cls_i16_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sext.h a0, a0 |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: addi a0, a0, -48 |
| ; CHECK-NEXT: ret |
| %a = ashr i16 %x, 15 |
| %b = xor i16 %x, %a |
| %c = shl i16 %b, 1 |
| %d = or i16 %c, 1 |
| %e = call i16 @llvm.ctlz.i16(i16 %d, i1 true) |
| ret i16 %e |
| } |
| |
| define i32 @cls_i32(i32 %x) { |
| ; CHECK-LABEL: cls_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: clsw a0, a0 |
| ; CHECK-NEXT: ret |
| %a = ashr i32 %x, 31 |
| %b = xor i32 %x, %a |
| %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) |
| %d = sub i32 %c, 1 |
| ret i32 %d |
| } |
| |
| define i32 @cls_i32_2(i32 %x) { |
| ; CHECK-LABEL: cls_i32_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: clsw a0, a0 |
| ; CHECK-NEXT: ret |
| %a = ashr i32 %x, 31 |
| %b = xor i32 %x, %a |
| %c = shl i32 %b, 1 |
| %d = or i32 %c, 1 |
| %e = call i32 @llvm.ctlz.i32(i32 %d, i1 true) |
| ret i32 %e |
| } |
| |
| ; The result is in the range [1-31], so we don't need an andi after the cls. |
| define i32 @cls_i32_knownbits(i32 %x) { |
| ; CHECK-LABEL: cls_i32_knownbits: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: clsw a0, a0 |
| ; CHECK-NEXT: ret |
| %a = ashr i32 %x, 31 |
| %b = xor i32 %x, %a |
| %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) |
| %d = sub i32 %c, 1 |
| %e = and i32 %d, 31 |
| ret i32 %e |
| } |
| |
| ; There are at least 16 redundant sign bits so we don't need an ori after the clsw. |
| define i32 @cls_i32_knownbits_2(i16 signext %x) { |
| ; CHECK-LABEL: cls_i32_knownbits_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: clsw a0, a0 |
| ; CHECK-NEXT: ret |
| %sext = sext i16 %x to i32 |
| %a = ashr i32 %sext, 31 |
| %b = xor i32 %sext, %a |
| %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) |
| %d = sub i32 %c, 1 |
| %e = or i32 %d, 16 |
| ret i32 %e |
| } |
| |
| ; There are at least 24 redundant sign bits so we don't need an ori after the clsw. |
| define i32 @cls_i32_knownbits_3(i8 signext %x) { |
| ; CHECK-LABEL: cls_i32_knownbits_3: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: clsw a0, a0 |
| ; CHECK-NEXT: ret |
| %sext = sext i8 %x to i32 |
| %a = ashr i32 %sext, 31 |
| %b = xor i32 %sext, %a |
| %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) |
| %d = sub i32 %c, 1 |
| %e = or i32 %d, 24 |
| ret i32 %e |
| } |
| |
| ; Negative test. We only know there is at least 1 redundant sign bit. We can't |
| ; remove the ori. |
| define i32 @cls_i32_knownbits_4(i32 signext %x) { |
| ; CHECK-LABEL: cls_i32_knownbits_4: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: slli a0, a0, 33 |
| ; CHECK-NEXT: srai a0, a0, 33 |
| ; CHECK-NEXT: clsw a0, a0 |
| ; CHECK-NEXT: ori a0, a0, 1 |
| ; CHECK-NEXT: ret |
| %shl = shl i32 %x, 1 |
| %ashr = ashr i32 %shl, 1 |
| %a = ashr i32 %ashr, 31 |
| %b = xor i32 %ashr, %a |
| %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) |
| %d = sub i32 %c, 1 |
| %e = or i32 %d, 1 |
| ret i32 %e |
| } |
| |
| define i64 @cls_i64(i64 %x) { |
| ; CHECK-LABEL: cls_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: ret |
| %a = ashr i64 %x, 63 |
| %b = xor i64 %x, %a |
| %c = call i64 @llvm.ctlz.i64(i64 %b, i1 false) |
| %d = sub i64 %c, 1 |
| ret i64 %d |
| } |
| |
| define i64 @cls_i64_2(i64 %x) { |
| ; CHECK-LABEL: cls_i64_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: ret |
| %a = ashr i64 %x, 63 |
| %b = xor i64 %x, %a |
| %c = shl i64 %b, 1 |
| %d = or i64 %c, 1 |
| %e = call i64 @llvm.ctlz.i64(i64 %d, i1 true) |
| ret i64 %e |
| } |
| |
| define i128 @slx_i128(i128 %x, i128 %y) { |
| ; CHECK-LABEL: slx_i128: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sll a3, a0, a2 |
| ; CHECK-NEXT: slx a1, a0, a2 |
| ; CHECK-NEXT: mv a0, a3 |
| ; CHECK-NEXT: ret |
| %a = and i128 %y, 63 |
| %b = shl i128 %x, %a |
| ret i128 %b |
| } |
| |
| define i128 @slxi_i128(i128 %x) { |
| ; CHECK-LABEL: slxi_i128: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: li a2, 49 |
| ; CHECK-NEXT: slx a1, a0, a2 |
| ; CHECK-NEXT: slli a0, a0, 49 |
| ; CHECK-NEXT: ret |
| %a = shl i128 %x, 49 |
| ret i128 %a |
| } |
| |
| define i128 @srx_i128(i128 %x, i128 %y) { |
| ; CHECK-LABEL: srx_i128: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: srl a3, a1, a2 |
| ; CHECK-NEXT: srx a0, a1, a2 |
| ; CHECK-NEXT: mv a1, a3 |
| ; CHECK-NEXT: ret |
| %a = and i128 %y, 63 |
| %b = lshr i128 %x, %a |
| ret i128 %b |
| } |
| |
| ; FIXME: Using srx instead of slx would avoid the mv. |
| define i128 @srxi_i128(i128 %x) { |
| ; CHECK-LABEL: srxi_i128: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: mv a2, a1 |
| ; CHECK-NEXT: li a3, 15 |
| ; CHECK-NEXT: srli a1, a1, 49 |
| ; CHECK-NEXT: slx a2, a0, a3 |
| ; CHECK-NEXT: mv a0, a2 |
| ; CHECK-NEXT: ret |
| %a = lshr i128 %x, 49 |
| ret i128 %a |
| } |
