| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+zbb -verify-machineinstrs \ |
| ; RUN: < %s | FileCheck %s |
| |
| define i32 @abs_i32(i32 %x) { |
| ; CHECK-LABEL: abs_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: abs a0, a0 |
| ; CHECK-NEXT: ret |
| %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) |
| ret i32 %abs |
| } |
| |
| define i64 @abs_i64(i64 %x) { |
| ; CHECK-LABEL: abs_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: bgez a1, .LBB1_2 |
| ; CHECK-NEXT: # %bb.1: |
| ; CHECK-NEXT: snez a2, a0 |
| ; CHECK-NEXT: neg a0, a0 |
| ; CHECK-NEXT: neg a1, a1 |
| ; CHECK-NEXT: sub a1, a1, a2 |
| ; CHECK-NEXT: .LBB1_2: |
| ; CHECK-NEXT: ret |
| %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) |
| ret i64 %abs |
| } |
| |
| ; Make sure we prefer li over pli |
| define i32 @li_imm() { |
| ; CHECK-LABEL: li_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: li a0, -1 |
| ; CHECK-NEXT: ret |
| ret i32 -1 |
| } |
| |
| define i32 @pli_b_i32(ptr %p) { |
| ; CHECK-LABEL: pli_b_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pli.b a0, 5 |
| ; CHECK-NEXT: ret |
| ret i32 u0x05050505 |
| } |
| |
| define i32 @pli_h_i32(ptr %p) { |
| ; CHECK-LABEL: pli_h_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pli.h a0, -64 |
| ; CHECK-NEXT: ret |
| ret i32 u0xffc0ffc0 |
| } |
| |
| define void @pli_b_store_i32(ptr %p) { |
| ; CHECK-LABEL: pli_b_store_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pli.b a1, 65 |
| ; CHECK-NEXT: sw a1, 0(a0) |
| ; CHECK-NEXT: ret |
| store i32 u0x41414141, ptr %p |
| ret void |
| } |
| |
| define i32 @pack_i32(i32 %a, i32 %b) nounwind { |
| ; CHECK-LABEL: pack_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pack a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %shl = and i32 %a, 65535 |
| %shl1 = shl i32 %b, 16 |
| %or = or i32 %shl1, %shl |
| ret i32 %or |
| } |
| |
| define i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind { |
| ; CHECK-LABEL: pack_i32_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pack a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %zexta = zext i16 %a to i32 |
| %zextb = zext i16 %b to i32 |
| %shl1 = shl i32 %zextb, 16 |
| %or = or i32 %shl1, %zexta |
| ret i32 %or |
| } |
| |
| define i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 %2) { |
| ; CHECK-LABEL: pack_i32_3: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: pack a0, a1, a0 |
| ; CHECK-NEXT: add a0, a0, a2 |
| ; CHECK-NEXT: ret |
| %4 = zext i16 %0 to i32 |
| %5 = shl nuw i32 %4, 16 |
| %6 = zext i16 %1 to i32 |
| %7 = or i32 %5, %6 |
| %8 = add i32 %7, %2 |
| ret i32 %8 |
| } |
| |
| define i8 @cls_i8(i8 %x) { |
| ; CHECK-LABEL: cls_i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sext.b a0, a0 |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: addi a0, a0, -24 |
| ; CHECK-NEXT: ret |
| %a = ashr i8 %x, 7 |
| %b = xor i8 %x, %a |
| %c = call i8 @llvm.ctlz.i8(i8 %b, i1 false) |
| %d = sub i8 %c, 1 |
| ret i8 %d |
| } |
| |
| define i8 @cls_i8_2(i8 %x) { |
| ; CHECK-LABEL: cls_i8_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sext.b a0, a0 |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: addi a0, a0, -24 |
| ; CHECK-NEXT: ret |
| %a = ashr i8 %x, 7 |
| %b = xor i8 %x, %a |
| %c = shl i8 %b, 1 |
| %d = or i8 %c, 1 |
| %e = call i8 @llvm.ctlz.i8(i8 %d, i1 true) |
| ret i8 %e |
| } |
| |
| define i16 @cls_i16(i16 %x) { |
| ; CHECK-LABEL: cls_i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sext.h a0, a0 |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: addi a0, a0, -16 |
| ; CHECK-NEXT: ret |
| %a = ashr i16 %x, 15 |
| %b = xor i16 %x, %a |
| %c = call i16 @llvm.ctlz.i16(i16 %b, i1 false) |
| %d = sub i16 %c, 1 |
| ret i16 %d |
| } |
| |
| define i16 @cls_i16_2(i16 %x) { |
| ; CHECK-LABEL: cls_i16_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sext.h a0, a0 |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: addi a0, a0, -16 |
| ; CHECK-NEXT: ret |
| %a = ashr i16 %x, 15 |
| %b = xor i16 %x, %a |
| %c = shl i16 %b, 1 |
| %d = or i16 %c, 1 |
| %e = call i16 @llvm.ctlz.i16(i16 %d, i1 true) |
| ret i16 %e |
| } |
| |
| define i32 @cls_i32(i32 %x) { |
| ; CHECK-LABEL: cls_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: ret |
| %a = ashr i32 %x, 31 |
| %b = xor i32 %x, %a |
| %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) |
| %d = sub i32 %c, 1 |
| ret i32 %d |
| } |
| |
| define i32 @cls_i32_2(i32 %x) { |
| ; CHECK-LABEL: cls_i32_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: cls a0, a0 |
| ; CHECK-NEXT: ret |
| %a = ashr i32 %x, 31 |
| %b = xor i32 %x, %a |
| %c = shl i32 %b, 1 |
| %d = or i32 %c, 1 |
| %e = call i32 @llvm.ctlz.i32(i32 %d, i1 true) |
| ret i32 %e |
| } |
| |
| define i64 @cls_i64(i64 %x) { |
| ; CHECK-LABEL: cls_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: srai a2, a1, 31 |
| ; CHECK-NEXT: bne a1, a2, .LBB15_2 |
| ; CHECK-NEXT: # %bb.1: |
| ; CHECK-NEXT: xor a0, a0, a2 |
| ; CHECK-NEXT: clz a0, a0 |
| ; CHECK-NEXT: addi a1, a0, 32 |
| ; CHECK-NEXT: j .LBB15_3 |
| ; CHECK-NEXT: .LBB15_2: |
| ; CHECK-NEXT: xor a1, a1, a2 |
| ; CHECK-NEXT: clz a1, a1 |
| ; CHECK-NEXT: .LBB15_3: |
| ; CHECK-NEXT: addi a0, a1, -1 |
| ; CHECK-NEXT: snez a1, a1 |
| ; CHECK-NEXT: addi a1, a1, -1 |
| ; CHECK-NEXT: ret |
| %a = ashr i64 %x, 63 |
| %b = xor i64 %x, %a |
| %c = call i64 @llvm.ctlz.i64(i64 %b, i1 false) |
| %d = sub i64 %c, 1 |
| ret i64 %d |
| } |
| |
| define i64 @cls_i64_2(i64 %x) { |
| ; CHECK-LABEL: cls_i64_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: srai a2, a1, 31 |
| ; CHECK-NEXT: xor a0, a0, a2 |
| ; CHECK-NEXT: xor a1, a1, a2 |
| ; CHECK-NEXT: li a2, 1 |
| ; CHECK-NEXT: slx a1, a0, a2 |
| ; CHECK-NEXT: bnez a1, .LBB16_2 |
| ; CHECK-NEXT: # %bb.1: |
| ; CHECK-NEXT: slli a0, a0, 1 |
| ; CHECK-NEXT: addi a0, a0, 1 |
| ; CHECK-NEXT: clz a0, a0 |
| ; CHECK-NEXT: addi a0, a0, 32 |
| ; CHECK-NEXT: li a1, 0 |
| ; CHECK-NEXT: ret |
| ; CHECK-NEXT: .LBB16_2: |
| ; CHECK-NEXT: clz a0, a1 |
| ; CHECK-NEXT: li a1, 0 |
| ; CHECK-NEXT: ret |
| %a = ashr i64 %x, 63 |
| %b = xor i64 %x, %a |
| %c = shl i64 %b, 1 |
| %d = or i64 %c, 1 |
| %e = call i64 @llvm.ctlz.i64(i64 %d, i1 true) |
| ret i64 %e |
| } |
| |
| define i64 @slx_i64(i64 %x, i64 %y) { |
| ; CHECK-LABEL: slx_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sll a3, a0, a2 |
| ; CHECK-NEXT: slx a1, a0, a2 |
| ; CHECK-NEXT: mv a0, a3 |
| ; CHECK-NEXT: ret |
| %a = and i64 %y, 31 |
| %b = shl i64 %x, %a |
| ret i64 %b |
| } |
| |
| define i64 @slxi_i64(i64 %x) { |
| ; CHECK-LABEL: slxi_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: li a2, 25 |
| ; CHECK-NEXT: slx a1, a0, a2 |
| ; CHECK-NEXT: slli a0, a0, 25 |
| ; CHECK-NEXT: ret |
| %a = shl i64 %x, 25 |
| ret i64 %a |
| } |
| |
| define i64 @srx_i64(i64 %x, i64 %y) { |
| ; CHECK-LABEL: srx_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: srl a3, a1, a2 |
| ; CHECK-NEXT: srx a0, a1, a2 |
| ; CHECK-NEXT: mv a1, a3 |
| ; CHECK-NEXT: ret |
| %a = and i64 %y, 31 |
| %b = lshr i64 %x, %a |
| ret i64 %b |
| } |
| |
| ; FIXME: Using srx instead of slx would avoid the mv. |
| define i64 @srxi_i64(i64 %x) { |
| ; CHECK-LABEL: srxi_i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: mv a2, a1 |
| ; CHECK-NEXT: li a3, 7 |
| ; CHECK-NEXT: srli a1, a1, 25 |
| ; CHECK-NEXT: slx a2, a0, a3 |
| ; CHECK-NEXT: mv a0, a2 |
| ; CHECK-NEXT: ret |
| %a = lshr i64 %x, 25 |
| ret i64 %a |
| } |
| |
| define i8 @shlsat_i8(i8 %a, i8 %b) { |
| ; CHECK-LABEL: shlsat_i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: zext.b a1, a1 |
| ; CHECK-NEXT: slli a0, a0, 24 |
| ; CHECK-NEXT: ssha a0, a0, a1 |
| ; CHECK-NEXT: srai a0, a0, 24 |
| ; CHECK-NEXT: ret |
| %sshlsat = tail call i8 @llvm.sshl.sat.i8(i8 %a,i8 %b) |
| ret i8 %sshlsat |
| } |
| |
| define i16 @shlsat_i16(i16 %a, i16 %b) { |
| ; CHECK-LABEL: shlsat_i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: zext.h a1, a1 |
| ; CHECK-NEXT: slli a0, a0, 16 |
| ; CHECK-NEXT: ssha a0, a0, a1 |
| ; CHECK-NEXT: srai a0, a0, 16 |
| ; CHECK-NEXT: ret |
| %sshlsat = tail call i16 @llvm.sshl.sat.i16(i16 %a,i16 %b) |
| ret i16 %sshlsat |
| } |
| |
| define i32 @shlsat_i32(i32 %a, i32 %b) { |
| ; CHECK-LABEL: shlsat_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: ssha a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %sshlsat = tail call i32 @llvm.sshl.sat.i32(i32 %a,i32 %b) |
| ret i32 %sshlsat |
| } |
| |
| define i8 @sadd_i8(i8 %x, i8 %y) { |
| ; CHECK-LABEL: sadd_i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: slli a1, a1, 24 |
| ; CHECK-NEXT: slli a0, a0, 24 |
| ; CHECK-NEXT: sadd a0, a0, a1 |
| ; CHECK-NEXT: srai a0, a0, 24 |
| ; CHECK-NEXT: ret |
| %a = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y) |
| ret i8 %a |
| } |
| |
| define i16 @sadd_i16(i16 %x, i16 %y) { |
| ; CHECK-LABEL: sadd_i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: slli a1, a1, 16 |
| ; CHECK-NEXT: slli a0, a0, 16 |
| ; CHECK-NEXT: sadd a0, a0, a1 |
| ; CHECK-NEXT: srai a0, a0, 16 |
| ; CHECK-NEXT: ret |
| %a = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y) |
| ret i16 %a |
| } |
| |
| define i32 @sadd_i32(i32 %x, i32 %y) { |
| ; CHECK-LABEL: sadd_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: sadd a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %a = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y) |
| ret i32 %a |
| } |
| |
| define i8 @ssub_i8(i8 %x, i8 %y) { |
| ; CHECK-LABEL: ssub_i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: slli a1, a1, 24 |
| ; CHECK-NEXT: slli a0, a0, 24 |
| ; CHECK-NEXT: ssub a0, a0, a1 |
| ; CHECK-NEXT: srai a0, a0, 24 |
| ; CHECK-NEXT: ret |
| %a = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y) |
| ret i8 %a |
| } |
| |
| define i16 @ssub_i16(i16 %x, i16 %y) { |
| ; CHECK-LABEL: ssub_i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: slli a1, a1, 16 |
| ; CHECK-NEXT: slli a0, a0, 16 |
| ; CHECK-NEXT: ssub a0, a0, a1 |
| ; CHECK-NEXT: srai a0, a0, 16 |
| ; CHECK-NEXT: ret |
| %a = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y) |
| ret i16 %a |
| } |
| |
| define i32 @ssub_i32(i32 %x, i32 %y) { |
| ; CHECK-LABEL: ssub_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: ssub a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %a = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y) |
| ret i32 %a |
| } |
| |
| define i8 @uadd_i8(i8 %x, i8 %y) { |
| ; CHECK-LABEL: uadd_i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: zext.b a1, a1 |
| ; CHECK-NEXT: zext.b a0, a0 |
| ; CHECK-NEXT: add a0, a0, a1 |
| ; CHECK-NEXT: li a1, 255 |
| ; CHECK-NEXT: minu a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %a = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y) |
| ret i8 %a |
| } |
| |
| define i16 @uadd_i16(i16 %x, i16 %y) { |
| ; CHECK-LABEL: uadd_i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: zext.h a1, a1 |
| ; CHECK-NEXT: zext.h a0, a0 |
| ; CHECK-NEXT: add a0, a0, a1 |
| ; CHECK-NEXT: lui a1, 16 |
| ; CHECK-NEXT: addi a1, a1, -1 |
| ; CHECK-NEXT: minu a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %a = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y) |
| ret i16 %a |
| } |
| |
| define i32 @uadd_i32(i32 %x, i32 %y) { |
| ; CHECK-LABEL: uadd_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: saddu a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %a = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y) |
| ret i32 %a |
| } |
| |
| define i8 @usub_i8(i8 %x, i8 %y) { |
| ; CHECK-LABEL: usub_i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: zext.b a1, a1 |
| ; CHECK-NEXT: zext.b a0, a0 |
| ; CHECK-NEXT: ssubu a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %a = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y) |
| ret i8 %a |
| } |
| |
| define i16 @usub_i16(i16 %x, i16 %y) { |
| ; CHECK-LABEL: usub_i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: zext.h a1, a1 |
| ; CHECK-NEXT: zext.h a0, a0 |
| ; CHECK-NEXT: ssubu a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %a = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y) |
| ret i16 %a |
| } |
| |
| define i32 @usub_i32(i32 %x, i32 %y) { |
| ; CHECK-LABEL: usub_i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: ssubu a0, a0, a1 |
| ; CHECK-NEXT: ret |
| %a = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y) |
| ret i32 %a |
| } |
