llvm/test/CodeGen/RISCV/optimize-cond-branch-undef.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=riscv64 -run-pass=peephole-opt -o - %s | FileCheck %s

# A conditional branch on an undef register with no def must not crash the
# peephole optimizer while it checks whether the operand is a load-immediate.
---
name: cond_branch_undef
tracksRegLiveness: true
body: |
  ; CHECK-LABEL: name: cond_branch_undef
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $x10
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
  ; CHECK-NEXT:   BLT undef %1:gpr, [[COPY]], %bb.1
  ; CHECK-NEXT:   PseudoBR %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   PseudoRET
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   PseudoRET
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $x10
    %0:gpr = COPY $x10
    BLT undef %1:gpr, %0, %bb.1
    PseudoBR %bb.2

  bb.1:
    PseudoRET

  bb.2:
    PseudoRET
...