llvm/test/CodeGen/RISCV/machine-outliner-debug-codegen.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --filter "SLLI|SRAI|ADDI|XOR|ADD|JALR|PseudoCALLReg" --version 5
# The two runs intentionally use the same check prefix: debug instructions
# must not change outlining decisions, calls, or outlined-function numbering.
# `critical` is intentionally too short to outline in both runs;
# the debug operands in a0/a1/a2 exercise candidate liveness.
# RUN: llc -mtriple=riscv32-unknown-elf -run-pass=machine-outliner \
# RUN:   -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
# RUN: llc -mtriple=riscv32-unknown-elf \
# RUN:   -run-pass=mir-strip-debug,machine-outliner \
# RUN:   -mir-strip-debugify-only=0 -verify-machineinstrs %s -o - | \
# RUN:   FileCheck %s --check-prefix=CHECK

--- |
  define void @critical() { ret void }
  define void @a0() { ret void }
  define void @a1() { ret void }
  define void @a2() { ret void }
  define void @b0() { ret void }
  define void @b1() { ret void }
  define void @b2() { ret void }
  define void @c0() { ret void }
  define void @c1() { ret void }
  define void @c2() { ret void }
  define void @d0() { ret void }
  define void @d1() { ret void }
  define void @d2() { ret void }

...
---
name:            critical
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: critical
  ; CHECK: bb.0:
  ; CHECK: bb.1:
  bb.0:
    liveins: $x7, $x15
    DBG_VALUE $x15, $noreg
    $x12 = DIV $x7, $x15

  bb.1:
    PseudoRET
...
---
name:            a0
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: a0
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_3, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 1
    $x11 = SLLI $x10, 10
    DBG_VALUE $x5, $noreg
    $x10 = SRAI $x11, 21
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 10
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 1
    PseudoRET implicit $x10
...
---
name:            a1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: a1
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_3, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 2
    $x11 = SLLI $x10, 10
    DBG_VALUE $x5, $noreg
    $x10 = SRAI $x11, 21
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 10
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 2
    PseudoRET implicit $x10
...
---
name:            a2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: a2
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_3, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 3
    $x11 = SLLI $x10, 10
    DBG_VALUE $x5, $noreg
    $x10 = SRAI $x11, 21
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 10
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 3
    PseudoRET implicit $x10
...
---
name:            b0
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: b0
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 4
    $x11 = SLLI $x10, 21
    $x10 = SRAI $x11, 21
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 21
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 4
    PseudoRET implicit $x10
...
---
name:            b1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: b1
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 5
    $x11 = SLLI $x10, 21
    $x10 = SRAI $x11, 21
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 21
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 5
    PseudoRET implicit $x10
...
---
name:            b2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: b2
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 6
    $x11 = SLLI $x10, 21
    $x10 = SRAI $x11, 21
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 21
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 6
    PseudoRET implicit $x10
...
---
name:            c0
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: c0
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 7
    $x11 = SLLI $x10, 3
    $x10 = SRAI $x11, 3
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 3
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 7
    PseudoRET implicit $x10
...
---
name:            c1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: c1
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 8
    $x11 = SLLI $x10, 3
    $x10 = SRAI $x11, 3
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 3
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 8
    PseudoRET implicit $x10
...
---
name:            c2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: c2
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_1, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 9
    $x11 = SLLI $x10, 3
    $x10 = SRAI $x11, 3
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 3
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 9
    PseudoRET implicit $x10
...
---
name:            d0
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: d0
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_2, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 10
    $x11 = SLLI $x10, 18
    $x10 = SRAI $x11, 18
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 18
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 10
    PseudoRET implicit $x10
...
---
name:            d1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: d1
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_2, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 11
    $x11 = SLLI $x10, 18
    $x10 = SRAI $x11, 18
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 18
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 11
    PseudoRET implicit $x10
...
---
name:            d2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x10
    ; CHECK-LABEL: name: d2
    ; CHECK: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_2, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit-def $x13, implicit-def $x14, implicit $x10
    ; CHECK-NEXT: $x0 = ADDI $x0, 12
    $x11 = SLLI $x10, 18
    $x10 = SRAI $x11, 18
    $x11 = SRAI $x11, 31
    $x12 = ADDI $x10, 18
    $x13 = XOR $x12, $x11
    $x14 = ADD $x13, $x10
    $x0 = ADDI $x0, 12
    PseudoRET implicit $x10
...