llvm/test/CodeGen/RISCV/machine-outliner-call-fallthrough.mir

# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefix=RV32 %s
# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefix=RV64 %s

# Check a normal outlined call at the end of a block that falls through to its
# successor. PseudoCALLReg is a returning call and must not be a barrier.

---
name:            outline_fallthrough_0
tracksRegLiveness: true
body:             |
  bb.0:
    successors: %bb.1
    liveins: $x10, $x11

    ; RV32-LABEL: name: outline_fallthrough_0
    ; RV32: bb.0:
    ; RV32: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0
    ; RV32: bb.1:
    ; RV32: PseudoRET implicit $x10
    ; RV64-LABEL: name: outline_fallthrough_0
    ; RV64: bb.0:
    ; RV64: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0
    ; RV64: bb.1:
    ; RV64: PseudoRET implicit $x10
    $x11 = ORI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x10 = SUB $x10, $x11

  bb.1:
    liveins: $x10
    PseudoRET implicit $x10

...
---
name:            outline_fallthrough_1
tracksRegLiveness: true
body:             |
  bb.0:
    successors: %bb.1
    liveins: $x10, $x11

    $x11 = ORI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x10 = SUB $x10, $x11

  bb.1:
    liveins: $x10
    PseudoRET implicit $x10

...
---
name:            outline_fallthrough_2
tracksRegLiveness: true
body:             |
  bb.0:
    successors: %bb.1
    liveins: $x10, $x11

    $x11 = ORI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x10 = SUB $x10, $x11

  bb.1:
    liveins: $x10
    PseudoRET implicit $x10

...