llvm/test/CodeGen/RISCV/llvm.sincos.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv64-linux-gnu -mattr=+d < %s | FileCheck %s --check-prefix=RV64
; RUN: llc -mtriple=riscv32-linux-gnu -mattr=+d < %s | FileCheck %s --check-prefix=RV32

; Test the llvm.sincos intrinsic lowering to the sincos libcalls, which glibc
; provides (sincosf/sincos/sincosl). RISC-V long double is fp128, so f128 uses
; sincosl.

define { float, float } @test_sincos_f32(float %a) nounwind {
; RV64-LABEL: test_sincos_f32:
; RV64:       # %bb.0:
; RV64-NEXT:    addi sp, sp, -16
; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT:    addi a0, sp, 4
; RV64-NEXT:    mv a1, sp
; RV64-NEXT:    call sincosf
; RV64-NEXT:    flw fa0, 4(sp)
; RV64-NEXT:    flw fa1, 0(sp)
; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT:    addi sp, sp, 16
; RV64-NEXT:    ret
;
; RV32-LABEL: test_sincos_f32:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT:    addi a0, sp, 8
; RV32-NEXT:    addi a1, sp, 4
; RV32-NEXT:    call sincosf
; RV32-NEXT:    flw fa0, 8(sp)
; RV32-NEXT:    flw fa1, 4(sp)
; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    ret
  %result = call { float, float } @llvm.sincos.f32(float %a)
  ret { float, float } %result
}

define { double, double } @test_sincos_f64(double %a) nounwind {
; RV64-LABEL: test_sincos_f64:
; RV64:       # %bb.0:
; RV64-NEXT:    addi sp, sp, -32
; RV64-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NEXT:    addi a0, sp, 16
; RV64-NEXT:    addi a1, sp, 8
; RV64-NEXT:    call sincos
; RV64-NEXT:    fld fa0, 16(sp)
; RV64-NEXT:    fld fa1, 8(sp)
; RV64-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NEXT:    addi sp, sp, 32
; RV64-NEXT:    ret
;
; RV32-LABEL: test_sincos_f64:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -32
; RV32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
; RV32-NEXT:    addi a0, sp, 16
; RV32-NEXT:    addi a1, sp, 8
; RV32-NEXT:    call sincos
; RV32-NEXT:    fld fa0, 16(sp)
; RV32-NEXT:    fld fa1, 8(sp)
; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT:    addi sp, sp, 32
; RV32-NEXT:    ret
  %result = call { double, double } @llvm.sincos.f64(double %a)
  ret { double, double } %result
}

define { fp128, fp128 } @test_sincos_f128(fp128 %a) nounwind {
; RV64-LABEL: test_sincos_f128:
; RV64:       # %bb.0:
; RV64-NEXT:    addi sp, sp, -48
; RV64-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
; RV64-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
; RV64-NEXT:    mv a4, a2
; RV64-NEXT:    mv s0, a0
; RV64-NEXT:    addi a2, sp, 16
; RV64-NEXT:    mv a3, sp
; RV64-NEXT:    mv a0, a1
; RV64-NEXT:    mv a1, a4
; RV64-NEXT:    call sincosl
; RV64-NEXT:    ld a0, 16(sp)
; RV64-NEXT:    ld a1, 24(sp)
; RV64-NEXT:    ld a2, 0(sp)
; RV64-NEXT:    ld a3, 8(sp)
; RV64-NEXT:    sd a0, 0(s0)
; RV64-NEXT:    sd a1, 8(s0)
; RV64-NEXT:    sd a2, 16(s0)
; RV64-NEXT:    sd a3, 24(s0)
; RV64-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
; RV64-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
; RV64-NEXT:    addi sp, sp, 48
; RV64-NEXT:    ret
;
; RV32-LABEL: test_sincos_f128:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -80
; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
; RV32-NEXT:    lw a4, 0(a1)
; RV32-NEXT:    lw a5, 4(a1)
; RV32-NEXT:    lw a6, 8(a1)
; RV32-NEXT:    lw a7, 12(a1)
; RV32-NEXT:    mv s0, a0
; RV32-NEXT:    addi a0, sp, 24
; RV32-NEXT:    addi a1, sp, 8
; RV32-NEXT:    addi a2, sp, 56
; RV32-NEXT:    addi a3, sp, 40
; RV32-NEXT:    sw a4, 8(sp)
; RV32-NEXT:    sw a5, 12(sp)
; RV32-NEXT:    sw a6, 16(sp)
; RV32-NEXT:    sw a7, 20(sp)
; RV32-NEXT:    call sincosl
; RV32-NEXT:    lw a0, 40(sp)
; RV32-NEXT:    lw a1, 44(sp)
; RV32-NEXT:    lw a2, 48(sp)
; RV32-NEXT:    lw a3, 52(sp)
; RV32-NEXT:    lw a4, 56(sp)
; RV32-NEXT:    lw a5, 60(sp)
; RV32-NEXT:    lw a6, 64(sp)
; RV32-NEXT:    lw a7, 68(sp)
; RV32-NEXT:    sw a0, 16(s0)
; RV32-NEXT:    sw a1, 20(s0)
; RV32-NEXT:    sw a2, 24(s0)
; RV32-NEXT:    sw a3, 28(s0)
; RV32-NEXT:    sw a4, 0(s0)
; RV32-NEXT:    sw a5, 4(s0)
; RV32-NEXT:    sw a6, 8(s0)
; RV32-NEXT:    sw a7, 12(s0)
; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
; RV32-NEXT:    addi sp, sp, 80
; RV32-NEXT:    ret
  %result = call { fp128, fp128 } @llvm.sincos.f128(fp128 %a)
  ret { fp128, fp128 } %result
}