llvm/test/CodeGen/RISCV/fadd-fmul-dagcombine.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 < %s | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+f < %s | FileCheck -check-prefix=RV32IF %s

; Chains of FADDs of the same value can fold into a multiplication. RV32I
; expands FMUL to a libcall, so the fold's gating on FMUL legality is
; observable here; RV32IF has a legal FMUL for comparison.

define float @fadd_chain_to_fmul(float %a) nounwind {
; RV32I-LABEL: fadd_chain_to_fmul:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi sp, sp, -16
; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT:    lui a1, 263168
; RV32I-NEXT:    call __mulsf3
; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT:    addi sp, sp, 16
; RV32I-NEXT:    ret
;
; RV32IF-LABEL: fadd_chain_to_fmul:
; RV32IF:       # %bb.0:
; RV32IF-NEXT:    lui a0, 263168
; RV32IF-NEXT:    fmv.w.x fa5, a0
; RV32IF-NEXT:    fmul.s fa0, fa0, fa5
; RV32IF-NEXT:    ret
  %1 = fadd fast float %a, %a
  %2 = fadd fast float %1, %a
  ret float %2
}

define float @fmul_fadd_to_fmul(float %a) nounwind {
; RV32I-LABEL: fmul_fadd_to_fmul:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi sp, sp, -16
; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT:    lui a1, 264192
; RV32I-NEXT:    call __mulsf3
; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT:    addi sp, sp, 16
; RV32I-NEXT:    ret
;
; RV32IF-LABEL: fmul_fadd_to_fmul:
; RV32IF:       # %bb.0:
; RV32IF-NEXT:    lui a0, 264192
; RV32IF-NEXT:    fmv.w.x fa5, a0
; RV32IF-NEXT:    fmul.s fa0, fa0, fa5
; RV32IF-NEXT:    ret
  %1 = fmul fast float %a, 3.0
  %2 = fadd fast float %1, %a
  ret float %2
}