llvm/test/CodeGen/RISCV/expand-pseudo.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=riscv-expand-pseudo-pre-emit %s -o - \
# RUN:   | FileCheck %s --check-prefixes=RV32
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=riscv-expand-pseudo-pre-emit %s -o - \
# RUN:   | FileCheck %s --check-prefixes=RV64
# RUN: llc -mtriple=riscv32 -mattr=+d -passes=riscv-expand-pseudo-pre-emit %s -o - \
# RUN:   | FileCheck %s --check-prefixes=RV32
# RUN: llc -mtriple=riscv64 -mattr=+d -passes=riscv-expand-pseudo-pre-emit %s -o - \
# RUN:   | FileCheck %s --check-prefixes=RV64

--- |
  define void @test() {
    ret void
  }
...
---
name:            test
noVRegs:         true
body:             |
  bb.0:
    ; RV32-LABEL: name: test
    ; RV32: $f10_d = FCVT_D_W $x0, 0
    ; RV32-NEXT: PseudoRET
    ;
    ; RV64-LABEL: name: test
    ; RV64: $f10_d = FMV_D_X $x0
    ; RV64-NEXT: PseudoRET
    $f10_d = PseudoClearFPR64
    PseudoRET
...