llvm/test/CodeGen/RISCV/expand-atomic-pseudo.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=riscv32 -mattr=+a -run-pass=riscv-expand-pseudo-atomics \
# RUN:   %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+a -run-pass=riscv-expand-pseudo-atomics \
# RUN:   %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv32 -mattr=+a -passes=riscv-expand-pseudo-atomics \
# RUN:   %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+a -passes=riscv-expand-pseudo-atomics \
# RUN:   %s -o - | FileCheck %s

--- |
  define void @test() #0 {
    ret void
  }

  attributes #0 = { noinline optnone }
...
---
name:            test
tracksRegLiveness: true
noVRegs:         true
body:             |
  bb.0:
    liveins: $x10, $x11

    ; CHECK-LABEL: name: test
    ; CHECK: successors: %bb.1(0x80000000)
    ; CHECK-NEXT: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: .1:
    ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
    ; CHECK-NEXT: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: $x12 = LR_W $x10
    ; CHECK-NEXT: $x13 = AND $x12, $x11
    ; CHECK-NEXT: $x13 = XORI $x13, -1
    ; CHECK-NEXT: $x13 = SC_W $x13, $x10
    ; CHECK-NEXT: BNE $x13, $x0, %bb.1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: .2:
    ; CHECK-NEXT: PseudoRET
    early-clobber $x12, early-clobber $x13 = PseudoAtomicLoadNand32 $x10, $x11, 2
    PseudoRET
...