| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64 %s |
| ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32 %s |
| |
| define void @test_bitint_200_add(ptr %a, ptr %b, ptr %out) nounwind { |
| ; RV64-LABEL: test_bitint_200_add: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: ld t0, 0(a0) |
| ; RV64-NEXT: ld t1, 0(a1) |
| ; RV64-NEXT: ld t2, 8(a1) |
| ; RV64-NEXT: ld a7, 8(a0) |
| ; RV64-NEXT: ld a3, 16(a0) |
| ; RV64-NEXT: lbu a4, 24(a0) |
| ; RV64-NEXT: ld a6, 16(a1) |
| ; RV64-NEXT: lbu a5, 24(a1) |
| ; RV64-NEXT: add a0, t0, t1 |
| ; RV64-NEXT: add a1, a7, t2 |
| ; RV64-NEXT: sltu t0, a0, t0 |
| ; RV64-NEXT: add a1, a1, t0 |
| ; RV64-NEXT: beq a1, a7, .LBB0_2 |
| ; RV64-NEXT: # %bb.1: |
| ; RV64-NEXT: sltu t0, a1, a7 |
| ; RV64-NEXT: .LBB0_2: |
| ; RV64-NEXT: add a6, a3, a6 |
| ; RV64-NEXT: add a4, a4, a5 |
| ; RV64-NEXT: add t0, a6, t0 |
| ; RV64-NEXT: sltu a3, a6, a3 |
| ; RV64-NEXT: sltu a5, t0, a6 |
| ; RV64-NEXT: add a3, a4, a3 |
| ; RV64-NEXT: add a3, a3, a5 |
| ; RV64-NEXT: sd a0, 0(a2) |
| ; RV64-NEXT: sd a1, 8(a2) |
| ; RV64-NEXT: sd t0, 16(a2) |
| ; RV64-NEXT: sb a3, 24(a2) |
| ; RV64-NEXT: ret |
| ; |
| ; RV32-LABEL: test_bitint_200_add: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: lw a4, 0(a0) |
| ; RV32-NEXT: lw a3, 0(a1) |
| ; RV32-NEXT: lw a7, 4(a1) |
| ; RV32-NEXT: lw t2, 4(a0) |
| ; RV32-NEXT: lw t1, 8(a0) |
| ; RV32-NEXT: lw t0, 12(a0) |
| ; RV32-NEXT: lw a5, 8(a1) |
| ; RV32-NEXT: lw a6, 12(a1) |
| ; RV32-NEXT: add a3, a4, a3 |
| ; RV32-NEXT: add t3, t2, a7 |
| ; RV32-NEXT: sltu a7, a3, a4 |
| ; RV32-NEXT: add a4, t3, a7 |
| ; RV32-NEXT: beq a4, t2, .LBB0_2 |
| ; RV32-NEXT: # %bb.1: |
| ; RV32-NEXT: sltu a7, a4, t2 |
| ; RV32-NEXT: .LBB0_2: |
| ; RV32-NEXT: add t2, t1, a5 |
| ; RV32-NEXT: add a5, t2, a7 |
| ; RV32-NEXT: add a6, t0, a6 |
| ; RV32-NEXT: sltu t3, t2, t1 |
| ; RV32-NEXT: sltu t2, a5, t2 |
| ; RV32-NEXT: add a6, a6, t3 |
| ; RV32-NEXT: add a6, a6, t2 |
| ; RV32-NEXT: beq a6, t0, .LBB0_4 |
| ; RV32-NEXT: # %bb.3: |
| ; RV32-NEXT: sltu t4, a6, t0 |
| ; RV32-NEXT: j .LBB0_5 |
| ; RV32-NEXT: .LBB0_4: |
| ; RV32-NEXT: sltu t4, a5, t1 |
| ; RV32-NEXT: .LBB0_5: |
| ; RV32-NEXT: lw t3, 16(a0) |
| ; RV32-NEXT: lw t2, 20(a0) |
| ; RV32-NEXT: lw t6, 16(a1) |
| ; RV32-NEXT: lw t5, 20(a1) |
| ; RV32-NEXT: xor t1, a5, t1 |
| ; RV32-NEXT: xor t0, a6, t0 |
| ; RV32-NEXT: or t0, t1, t0 |
| ; RV32-NEXT: beqz t0, .LBB0_7 |
| ; RV32-NEXT: # %bb.6: |
| ; RV32-NEXT: mv a7, t4 |
| ; RV32-NEXT: .LBB0_7: |
| ; RV32-NEXT: lbu a0, 24(a0) |
| ; RV32-NEXT: add t6, t3, t6 |
| ; RV32-NEXT: lbu a1, 24(a1) |
| ; RV32-NEXT: add a7, t6, a7 |
| ; RV32-NEXT: add t4, t2, t5 |
| ; RV32-NEXT: sltu t1, t6, t3 |
| ; RV32-NEXT: sltu t3, a7, t6 |
| ; RV32-NEXT: add t4, t4, t1 |
| ; RV32-NEXT: add t0, t4, t3 |
| ; RV32-NEXT: sltu t5, t0, t4 |
| ; RV32-NEXT: and t3, t3, t5 |
| ; RV32-NEXT: beq t4, t2, .LBB0_9 |
| ; RV32-NEXT: # %bb.8: |
| ; RV32-NEXT: sltu t1, t4, t2 |
| ; RV32-NEXT: .LBB0_9: |
| ; RV32-NEXT: add a0, a0, a1 |
| ; RV32-NEXT: add t1, t1, t3 |
| ; RV32-NEXT: add a0, a0, t1 |
| ; RV32-NEXT: sw a3, 0(a2) |
| ; RV32-NEXT: sw a4, 4(a2) |
| ; RV32-NEXT: sw a5, 8(a2) |
| ; RV32-NEXT: sw a6, 12(a2) |
| ; RV32-NEXT: sw a7, 16(a2) |
| ; RV32-NEXT: sw t0, 20(a2) |
| ; RV32-NEXT: sb a0, 24(a2) |
| ; RV32-NEXT: ret |
| %1 = load i200, ptr %a, align 8 |
| %2 = load i200, ptr %b, align 8 |
| %3 = add i200 %1, %2 |
| store i200 %3, ptr %out, align 8 |
| ret void |
| } |
| |
| define void @test_bitint_200_to_float(ptr %in, ptr %out) nounwind { |
| ; RV64-LABEL: test_bitint_200_to_float: |
| ; RV64: # %bb.0: # %itofp-entry |
| ; RV64-NEXT: ld a4, 0(a0) |
| ; RV64-NEXT: ld a3, 8(a0) |
| ; RV64-NEXT: ld a5, 16(a0) |
| ; RV64-NEXT: lb a2, 24(a0) |
| ; RV64-NEXT: or a0, a3, a2 |
| ; RV64-NEXT: or a6, a4, a5 |
| ; RV64-NEXT: or a0, a6, a0 |
| ; RV64-NEXT: beqz a0, .LBB1_22 |
| ; RV64-NEXT: # %bb.1: # %itofp-if-end |
| ; RV64-NEXT: slli a0, a2, 56 |
| ; RV64-NEXT: srai a0, a0, 63 |
| ; RV64-NEXT: xor a5, a5, a0 |
| ; RV64-NEXT: xor a7, a2, a0 |
| ; RV64-NEXT: xor a6, a4, a0 |
| ; RV64-NEXT: sltu a4, a5, a0 |
| ; RV64-NEXT: sub a7, a7, a0 |
| ; RV64-NEXT: sltu t0, a6, a0 |
| ; RV64-NEXT: sub a7, a7, a4 |
| ; RV64-NEXT: xor a4, a3, a0 |
| ; RV64-NEXT: mv t1, t0 |
| ; RV64-NEXT: beqz a3, .LBB1_3 |
| ; RV64-NEXT: # %bb.2: # %itofp-if-end |
| ; RV64-NEXT: sltu t1, a4, a0 |
| ; RV64-NEXT: .LBB1_3: # %itofp-if-end |
| ; RV64-NEXT: sub a5, a5, a0 |
| ; RV64-NEXT: sub a3, a4, a0 |
| ; RV64-NEXT: sltu t2, a5, t1 |
| ; RV64-NEXT: sub a4, a5, t1 |
| ; RV64-NEXT: sub a3, a3, t0 |
| ; RV64-NEXT: sub a5, a7, t2 |
| ; RV64-NEXT: srli a7, a3, 8 |
| ; RV64-NEXT: slli t0, a4, 56 |
| ; RV64-NEXT: lui t1, 349525 |
| ; RV64-NEXT: or a7, t0, a7 |
| ; RV64-NEXT: addi t4, t1, 1365 |
| ; RV64-NEXT: slli t0, t4, 32 |
| ; RV64-NEXT: lui t1, 209715 |
| ; RV64-NEXT: add t4, t4, t0 |
| ; RV64-NEXT: addi t2, t1, 819 |
| ; RV64-NEXT: slli t0, t2, 32 |
| ; RV64-NEXT: lui t1, 61681 |
| ; RV64-NEXT: add t2, t2, t0 |
| ; RV64-NEXT: addi t3, t1, -241 |
| ; RV64-NEXT: slli t0, a5, 56 |
| ; RV64-NEXT: srli t1, a4, 8 |
| ; RV64-NEXT: or t0, t0, t1 |
| ; RV64-NEXT: slli t1, t3, 32 |
| ; RV64-NEXT: sub a6, a6, a0 |
| ; RV64-NEXT: add t3, t3, t1 |
| ; RV64-NEXT: bnez t0, .LBB1_5 |
| ; RV64-NEXT: # %bb.4: # %itofp-if-end |
| ; RV64-NEXT: srli t1, a7, 1 |
| ; RV64-NEXT: or t1, a7, t1 |
| ; RV64-NEXT: srli t5, t1, 2 |
| ; RV64-NEXT: or t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 4 |
| ; RV64-NEXT: or t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 8 |
| ; RV64-NEXT: or t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 16 |
| ; RV64-NEXT: or t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 32 |
| ; RV64-NEXT: or t1, t1, t5 |
| ; RV64-NEXT: not t1, t1 |
| ; RV64-NEXT: srli t5, t1, 1 |
| ; RV64-NEXT: and t5, t5, t4 |
| ; RV64-NEXT: sub t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 2 |
| ; RV64-NEXT: and t1, t1, t2 |
| ; RV64-NEXT: and t5, t5, t2 |
| ; RV64-NEXT: add t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 4 |
| ; RV64-NEXT: add t1, t1, t5 |
| ; RV64-NEXT: and t1, t1, t3 |
| ; RV64-NEXT: slli t5, t1, 8 |
| ; RV64-NEXT: add t1, t1, t5 |
| ; RV64-NEXT: slli t5, t1, 16 |
| ; RV64-NEXT: add t1, t1, t5 |
| ; RV64-NEXT: slli t5, t1, 32 |
| ; RV64-NEXT: add t1, t1, t5 |
| ; RV64-NEXT: srli t1, t1, 56 |
| ; RV64-NEXT: addi t1, t1, 64 |
| ; RV64-NEXT: j .LBB1_6 |
| ; RV64-NEXT: .LBB1_5: |
| ; RV64-NEXT: srli t1, t0, 1 |
| ; RV64-NEXT: or t1, t0, t1 |
| ; RV64-NEXT: srli t5, t1, 2 |
| ; RV64-NEXT: or t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 4 |
| ; RV64-NEXT: or t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 8 |
| ; RV64-NEXT: or t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 16 |
| ; RV64-NEXT: or t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 32 |
| ; RV64-NEXT: or t1, t1, t5 |
| ; RV64-NEXT: not t1, t1 |
| ; RV64-NEXT: srli t5, t1, 1 |
| ; RV64-NEXT: and t5, t5, t4 |
| ; RV64-NEXT: sub t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 2 |
| ; RV64-NEXT: and t1, t1, t2 |
| ; RV64-NEXT: and t5, t5, t2 |
| ; RV64-NEXT: add t1, t1, t5 |
| ; RV64-NEXT: srli t5, t1, 4 |
| ; RV64-NEXT: add t1, t1, t5 |
| ; RV64-NEXT: and t1, t1, t3 |
| ; RV64-NEXT: slli t5, t1, 8 |
| ; RV64-NEXT: add t1, t1, t5 |
| ; RV64-NEXT: slli t5, t1, 16 |
| ; RV64-NEXT: add t1, t1, t5 |
| ; RV64-NEXT: slli t5, t1, 32 |
| ; RV64-NEXT: add t1, t1, t5 |
| ; RV64-NEXT: srli t1, t1, 56 |
| ; RV64-NEXT: .LBB1_6: # %itofp-if-end |
| ; RV64-NEXT: slli t5, a3, 56 |
| ; RV64-NEXT: srli t6, a6, 8 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: bnez t5, .LBB1_8 |
| ; RV64-NEXT: # %bb.7: # %itofp-if-end |
| ; RV64-NEXT: slli t5, a6, 56 |
| ; RV64-NEXT: srli t6, t5, 1 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: srli t6, t5, 2 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: srli t6, t5, 4 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: srli t6, t5, 8 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: srli t6, t5, 16 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: srli t6, t5, 32 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: not t5, t5 |
| ; RV64-NEXT: srli t6, t5, 1 |
| ; RV64-NEXT: and t4, t6, t4 |
| ; RV64-NEXT: sub t4, t5, t4 |
| ; RV64-NEXT: srli t5, t4, 2 |
| ; RV64-NEXT: and t4, t4, t2 |
| ; RV64-NEXT: and t2, t5, t2 |
| ; RV64-NEXT: add t2, t4, t2 |
| ; RV64-NEXT: srli t4, t2, 4 |
| ; RV64-NEXT: add t2, t2, t4 |
| ; RV64-NEXT: and t2, t2, t3 |
| ; RV64-NEXT: slli t3, t2, 8 |
| ; RV64-NEXT: add t2, t2, t3 |
| ; RV64-NEXT: slli t3, t2, 16 |
| ; RV64-NEXT: add t2, t2, t3 |
| ; RV64-NEXT: slli t3, t2, 32 |
| ; RV64-NEXT: add t2, t2, t3 |
| ; RV64-NEXT: srli t2, t2, 56 |
| ; RV64-NEXT: addi t2, t2, 64 |
| ; RV64-NEXT: or a7, a7, t0 |
| ; RV64-NEXT: beqz a7, .LBB1_9 |
| ; RV64-NEXT: j .LBB1_10 |
| ; RV64-NEXT: .LBB1_8: |
| ; RV64-NEXT: srli t6, t5, 1 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: srli t6, t5, 2 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: srli t6, t5, 4 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: srli t6, t5, 8 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: srli t6, t5, 16 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: srli t6, t5, 32 |
| ; RV64-NEXT: or t5, t5, t6 |
| ; RV64-NEXT: not t5, t5 |
| ; RV64-NEXT: srli t6, t5, 1 |
| ; RV64-NEXT: and t4, t6, t4 |
| ; RV64-NEXT: sub t4, t5, t4 |
| ; RV64-NEXT: srli t5, t4, 2 |
| ; RV64-NEXT: and t4, t4, t2 |
| ; RV64-NEXT: and t2, t5, t2 |
| ; RV64-NEXT: add t2, t4, t2 |
| ; RV64-NEXT: srli t4, t2, 4 |
| ; RV64-NEXT: add t2, t2, t4 |
| ; RV64-NEXT: and t2, t2, t3 |
| ; RV64-NEXT: slli t3, t2, 8 |
| ; RV64-NEXT: add t2, t2, t3 |
| ; RV64-NEXT: slli t3, t2, 16 |
| ; RV64-NEXT: add t2, t2, t3 |
| ; RV64-NEXT: slli t3, t2, 32 |
| ; RV64-NEXT: add t2, t2, t3 |
| ; RV64-NEXT: srli t2, t2, 56 |
| ; RV64-NEXT: or a7, a7, t0 |
| ; RV64-NEXT: bnez a7, .LBB1_10 |
| ; RV64-NEXT: .LBB1_9: # %itofp-if-end |
| ; RV64-NEXT: addi t1, t2, 128 |
| ; RV64-NEXT: .LBB1_10: # %itofp-if-end |
| ; RV64-NEXT: addi sp, sp, -224 |
| ; RV64-NEXT: sd s0, 216(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s1, 208(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s2, 200(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: li a7, 200 |
| ; RV64-NEXT: sub t0, a7, t1 |
| ; RV64-NEXT: li a7, 199 |
| ; RV64-NEXT: li t2, 25 |
| ; RV64-NEXT: sub a7, a7, t1 |
| ; RV64-NEXT: blt t0, t2, .LBB1_23 |
| ; RV64-NEXT: # %bb.11: # %itofp-if-then4 |
| ; RV64-NEXT: li t2, 26 |
| ; RV64-NEXT: beq t0, t2, .LBB1_14 |
| ; RV64-NEXT: # %bb.12: # %itofp-if-then4 |
| ; RV64-NEXT: li t2, 25 |
| ; RV64-NEXT: beq t0, t2, .LBB1_25 |
| ; RV64-NEXT: # %bb.13: # %itofp-sw-default |
| ; RV64-NEXT: li t2, 174 |
| ; RV64-NEXT: sub t2, t2, t1 |
| ; RV64-NEXT: sd zero, 96(sp) |
| ; RV64-NEXT: sd zero, 104(sp) |
| ; RV64-NEXT: sd zero, 112(sp) |
| ; RV64-NEXT: sd zero, 120(sp) |
| ; RV64-NEXT: srli t3, t2, 3 |
| ; RV64-NEXT: zext.b t4, a5 |
| ; RV64-NEXT: andi t3, t3, 24 |
| ; RV64-NEXT: addi t5, sp, 64 |
| ; RV64-NEXT: sd a6, 64(sp) |
| ; RV64-NEXT: sd a3, 72(sp) |
| ; RV64-NEXT: sd a4, 80(sp) |
| ; RV64-NEXT: sd t4, 88(sp) |
| ; RV64-NEXT: add t3, t5, t3 |
| ; RV64-NEXT: ld t5, 16(t3) |
| ; RV64-NEXT: andi t6, t2, 63 |
| ; RV64-NEXT: ld t4, 8(t3) |
| ; RV64-NEXT: ld s0, 0(t3) |
| ; RV64-NEXT: xori t3, t6, 63 |
| ; RV64-NEXT: slli t5, t5, 1 |
| ; RV64-NEXT: addi t1, t1, 26 |
| ; RV64-NEXT: srli t6, t1, 3 |
| ; RV64-NEXT: sd zero, 0(sp) |
| ; RV64-NEXT: sd zero, 8(sp) |
| ; RV64-NEXT: sd zero, 16(sp) |
| ; RV64-NEXT: sd zero, 24(sp) |
| ; RV64-NEXT: andi t6, t6, 24 |
| ; RV64-NEXT: addi s1, sp, 32 |
| ; RV64-NEXT: sd a6, 32(sp) |
| ; RV64-NEXT: sd a3, 40(sp) |
| ; RV64-NEXT: sd a4, 48(sp) |
| ; RV64-NEXT: sd a5, 56(sp) |
| ; RV64-NEXT: sub a3, s1, t6 |
| ; RV64-NEXT: ld a4, 0(a3) |
| ; RV64-NEXT: ld a5, 8(a3) |
| ; RV64-NEXT: srl a6, t4, t2 |
| ; RV64-NEXT: sll t5, t5, t3 |
| ; RV64-NEXT: or t5, a6, t5 |
| ; RV64-NEXT: ld a6, 16(a3) |
| ; RV64-NEXT: srl t2, s0, t2 |
| ; RV64-NEXT: ld a3, 24(a3) |
| ; RV64-NEXT: sll t6, a5, t1 |
| ; RV64-NEXT: andi s0, t1, 63 |
| ; RV64-NEXT: srli s1, a4, 1 |
| ; RV64-NEXT: xori s0, s0, 63 |
| ; RV64-NEXT: srl s1, s1, s0 |
| ; RV64-NEXT: srli s2, a6, 1 |
| ; RV64-NEXT: sll a3, a3, t1 |
| ; RV64-NEXT: srl s2, s2, s0 |
| ; RV64-NEXT: or t6, t6, s1 |
| ; RV64-NEXT: or a3, a3, s2 |
| ; RV64-NEXT: slli t4, t4, 1 |
| ; RV64-NEXT: zext.b a3, a3 |
| ; RV64-NEXT: or a4, a6, a4 |
| ; RV64-NEXT: srli a5, a5, 1 |
| ; RV64-NEXT: sll a4, a4, t1 |
| ; RV64-NEXT: srl a5, a5, s0 |
| ; RV64-NEXT: or a3, t6, a3 |
| ; RV64-NEXT: or a4, a4, a5 |
| ; RV64-NEXT: sll a5, t4, t3 |
| ; RV64-NEXT: or a3, a4, a3 |
| ; RV64-NEXT: or a4, t2, a5 |
| ; RV64-NEXT: snez a3, a3 |
| ; RV64-NEXT: or a6, a4, a3 |
| ; RV64-NEXT: mv a3, t5 |
| ; RV64-NEXT: .LBB1_14: # %itofp-sw-epilog |
| ; RV64-NEXT: slli a4, a6, 61 |
| ; RV64-NEXT: srli a4, a4, 63 |
| ; RV64-NEXT: or a4, a6, a4 |
| ; RV64-NEXT: addi a4, a4, 1 |
| ; RV64-NEXT: seqz a5, a4 |
| ; RV64-NEXT: slli a6, a4, 37 |
| ; RV64-NEXT: add a3, a3, a5 |
| ; RV64-NEXT: bltz a6, .LBB1_24 |
| ; RV64-NEXT: # %bb.15: |
| ; RV64-NEXT: srli a4, a4, 2 |
| ; RV64-NEXT: slli a3, a3, 62 |
| ; RV64-NEXT: or a3, a4, a3 |
| ; RV64-NEXT: .LBB1_16: # %itofp-if-end26 |
| ; RV64-NEXT: mv t0, a7 |
| ; RV64-NEXT: .LBB1_17: # %itofp-if-end26 |
| ; RV64-NEXT: lui a4, 1046528 |
| ; RV64-NEXT: ld s0, 216(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s1, 208(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s2, 200(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: addi sp, sp, 224 |
| ; RV64-NEXT: bgez a2, .LBB1_20 |
| ; RV64-NEXT: # %bb.18: # %itofp-if-end26 |
| ; RV64-NEXT: li a2, 127 |
| ; RV64-NEXT: bgeu a2, a7, .LBB1_21 |
| ; RV64-NEXT: .LBB1_19: # %itofp-return |
| ; RV64-NEXT: sw a4, 0(a1) |
| ; RV64-NEXT: ret |
| ; RV64-NEXT: .LBB1_20: # %itofp-if-end26 |
| ; RV64-NEXT: lui a4, 522240 |
| ; RV64-NEXT: li a2, 127 |
| ; RV64-NEXT: bltu a2, a7, .LBB1_19 |
| ; RV64-NEXT: .LBB1_21: # %itofp-if-end26 |
| ; RV64-NEXT: lui a2, 524288 |
| ; RV64-NEXT: slli a3, a3, 41 |
| ; RV64-NEXT: slli t0, t0, 23 |
| ; RV64-NEXT: and a0, a0, a2 |
| ; RV64-NEXT: lui a2, 260096 |
| ; RV64-NEXT: srli a3, a3, 41 |
| ; RV64-NEXT: add a2, t0, a2 |
| ; RV64-NEXT: or a0, a3, a0 |
| ; RV64-NEXT: or a4, a0, a2 |
| ; RV64-NEXT: sw a4, 0(a1) |
| ; RV64-NEXT: ret |
| ; RV64-NEXT: .LBB1_22: |
| ; RV64-NEXT: sw zero, 0(a1) |
| ; RV64-NEXT: ret |
| ; RV64-NEXT: .LBB1_23: # %itofp-if-else |
| ; RV64-NEXT: addi a3, t1, -176 |
| ; RV64-NEXT: sd a6, 160(sp) |
| ; RV64-NEXT: addi a4, sp, 160 |
| ; RV64-NEXT: srli a5, a3, 3 |
| ; RV64-NEXT: andi a5, a5, 24 |
| ; RV64-NEXT: sd zero, 128(sp) |
| ; RV64-NEXT: sd zero, 136(sp) |
| ; RV64-NEXT: sd zero, 144(sp) |
| ; RV64-NEXT: sd zero, 152(sp) |
| ; RV64-NEXT: sub a4, a4, a5 |
| ; RV64-NEXT: ld a4, 0(a4) |
| ; RV64-NEXT: sll a3, a4, a3 |
| ; RV64-NEXT: j .LBB1_16 |
| ; RV64-NEXT: .LBB1_24: # %itofp-if-then20 |
| ; RV64-NEXT: srli a4, a4, 3 |
| ; RV64-NEXT: slli a3, a3, 61 |
| ; RV64-NEXT: or a3, a4, a3 |
| ; RV64-NEXT: j .LBB1_17 |
| ; RV64-NEXT: .LBB1_25: # %itofp-sw-bb |
| ; RV64-NEXT: srli a4, a6, 63 |
| ; RV64-NEXT: slli a3, a3, 1 |
| ; RV64-NEXT: or a3, a3, a4 |
| ; RV64-NEXT: slli a6, a6, 1 |
| ; RV64-NEXT: j .LBB1_14 |
| ; |
| ; RV32-LABEL: test_bitint_200_to_float: |
| ; RV32: # %bb.0: # %itofp-entry |
| ; RV32-NEXT: lw a4, 16(a0) |
| ; RV32-NEXT: lw a3, 20(a0) |
| ; RV32-NEXT: lbu a2, 24(a0) |
| ; RV32-NEXT: lw t0, 8(a0) |
| ; RV32-NEXT: lw t1, 0(a0) |
| ; RV32-NEXT: lw t5, 4(a0) |
| ; RV32-NEXT: lw t2, 12(a0) |
| ; RV32-NEXT: or a0, t0, a2 |
| ; RV32-NEXT: or a5, t1, a4 |
| ; RV32-NEXT: or a6, t5, a3 |
| ; RV32-NEXT: or a0, a5, a0 |
| ; RV32-NEXT: or a5, a6, t2 |
| ; RV32-NEXT: or a0, a0, a5 |
| ; RV32-NEXT: beqz a0, .LBB1_37 |
| ; RV32-NEXT: # %bb.1: # %itofp-if-end |
| ; RV32-NEXT: addi sp, sp, -224 |
| ; RV32-NEXT: sw s0, 220(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s1, 216(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s2, 212(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s3, 208(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s4, 204(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s5, 200(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s6, 196(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s7, 192(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: slli a2, a2, 24 |
| ; RV32-NEXT: srai a2, a2, 24 |
| ; RV32-NEXT: slli a0, a2, 24 |
| ; RV32-NEXT: srai s2, a0, 31 |
| ; RV32-NEXT: srai a0, a0, 24 |
| ; RV32-NEXT: slli a6, s2, 25 |
| ; RV32-NEXT: srli a0, a0, 7 |
| ; RV32-NEXT: xor a5, t0, s2 |
| ; RV32-NEXT: or a0, a0, a6 |
| ; RV32-NEXT: sltu a6, a5, s2 |
| ; RV32-NEXT: xor a7, t2, s2 |
| ; RV32-NEXT: mv t6, a6 |
| ; RV32-NEXT: beqz t2, .LBB1_3 |
| ; RV32-NEXT: # %bb.2: # %itofp-if-end |
| ; RV32-NEXT: sltu t6, a7, s2 |
| ; RV32-NEXT: .LBB1_3: # %itofp-if-end |
| ; RV32-NEXT: xor t4, t1, a0 |
| ; RV32-NEXT: sltu t3, t4, a0 |
| ; RV32-NEXT: xor s3, t5, s2 |
| ; RV32-NEXT: mv t1, t3 |
| ; RV32-NEXT: beqz t5, .LBB1_5 |
| ; RV32-NEXT: # %bb.4: # %itofp-if-end |
| ; RV32-NEXT: sltu t1, s3, s2 |
| ; RV32-NEXT: .LBB1_5: # %itofp-if-end |
| ; RV32-NEXT: or t2, t0, t2 |
| ; RV32-NEXT: mv t0, t1 |
| ; RV32-NEXT: beqz t2, .LBB1_7 |
| ; RV32-NEXT: # %bb.6: # %itofp-if-end |
| ; RV32-NEXT: mv t0, t6 |
| ; RV32-NEXT: .LBB1_7: # %itofp-if-end |
| ; RV32-NEXT: xor a4, a4, s2 |
| ; RV32-NEXT: xor s1, a3, s2 |
| ; RV32-NEXT: sltu s0, a4, s2 |
| ; RV32-NEXT: sub t2, s1, s2 |
| ; RV32-NEXT: sub a4, a4, s2 |
| ; RV32-NEXT: sub t2, t2, s0 |
| ; RV32-NEXT: sltu t5, a4, t0 |
| ; RV32-NEXT: seqz t6, t2 |
| ; RV32-NEXT: and t6, t6, t5 |
| ; RV32-NEXT: beqz a3, .LBB1_9 |
| ; RV32-NEXT: # %bb.8: # %itofp-if-end |
| ; RV32-NEXT: sltu s0, s1, s2 |
| ; RV32-NEXT: .LBB1_9: # %itofp-if-end |
| ; RV32-NEXT: xor a3, a2, s2 |
| ; RV32-NEXT: add s0, s2, s0 |
| ; RV32-NEXT: sub s1, a7, s2 |
| ; RV32-NEXT: sub a3, a3, s0 |
| ; RV32-NEXT: sub s0, a5, s2 |
| ; RV32-NEXT: sub a7, a3, t6 |
| ; RV32-NEXT: sub a3, s1, a6 |
| ; RV32-NEXT: sltu a5, s0, t1 |
| ; RV32-NEXT: sub a5, a3, a5 |
| ; RV32-NEXT: sub a3, t2, t5 |
| ; RV32-NEXT: sub a4, a4, t0 |
| ; RV32-NEXT: sub a6, s0, t1 |
| ; RV32-NEXT: srli t0, a4, 8 |
| ; RV32-NEXT: slli t1, a3, 24 |
| ; RV32-NEXT: or t1, t0, t1 |
| ; RV32-NEXT: lui t5, 349525 |
| ; RV32-NEXT: addi t5, t5, 1365 |
| ; RV32-NEXT: lui t0, 209715 |
| ; RV32-NEXT: srli t2, a3, 8 |
| ; RV32-NEXT: slli t6, a7, 24 |
| ; RV32-NEXT: lui s1, 61681 |
| ; RV32-NEXT: or t2, t6, t2 |
| ; RV32-NEXT: addi s0, t0, 819 |
| ; RV32-NEXT: addi t6, s1, -241 |
| ; RV32-NEXT: bnez t2, .LBB1_11 |
| ; RV32-NEXT: # %bb.10: # %itofp-if-end |
| ; RV32-NEXT: srli t0, t1, 1 |
| ; RV32-NEXT: or t0, t1, t0 |
| ; RV32-NEXT: srli s1, t0, 2 |
| ; RV32-NEXT: or t0, t0, s1 |
| ; RV32-NEXT: srli s1, t0, 4 |
| ; RV32-NEXT: or t0, t0, s1 |
| ; RV32-NEXT: srli s1, t0, 8 |
| ; RV32-NEXT: or t0, t0, s1 |
| ; RV32-NEXT: srli s1, t0, 16 |
| ; RV32-NEXT: or t0, t0, s1 |
| ; RV32-NEXT: not t0, t0 |
| ; RV32-NEXT: srli s1, t0, 1 |
| ; RV32-NEXT: and s1, s1, t5 |
| ; RV32-NEXT: sub t0, t0, s1 |
| ; RV32-NEXT: srli s1, t0, 2 |
| ; RV32-NEXT: and t0, t0, s0 |
| ; RV32-NEXT: and s1, s1, s0 |
| ; RV32-NEXT: add t0, t0, s1 |
| ; RV32-NEXT: srli s1, t0, 4 |
| ; RV32-NEXT: add t0, t0, s1 |
| ; RV32-NEXT: and t0, t0, t6 |
| ; RV32-NEXT: slli s1, t0, 8 |
| ; RV32-NEXT: add t0, t0, s1 |
| ; RV32-NEXT: slli s1, t0, 16 |
| ; RV32-NEXT: add t0, t0, s1 |
| ; RV32-NEXT: srli t0, t0, 24 |
| ; RV32-NEXT: addi t0, t0, 32 |
| ; RV32-NEXT: j .LBB1_12 |
| ; RV32-NEXT: .LBB1_11: |
| ; RV32-NEXT: srli t0, t2, 1 |
| ; RV32-NEXT: or t0, t2, t0 |
| ; RV32-NEXT: srli s1, t0, 2 |
| ; RV32-NEXT: or t0, t0, s1 |
| ; RV32-NEXT: srli s1, t0, 4 |
| ; RV32-NEXT: or t0, t0, s1 |
| ; RV32-NEXT: srli s1, t0, 8 |
| ; RV32-NEXT: or t0, t0, s1 |
| ; RV32-NEXT: srli s1, t0, 16 |
| ; RV32-NEXT: or t0, t0, s1 |
| ; RV32-NEXT: not t0, t0 |
| ; RV32-NEXT: srli s1, t0, 1 |
| ; RV32-NEXT: and s1, s1, t5 |
| ; RV32-NEXT: sub t0, t0, s1 |
| ; RV32-NEXT: srli s1, t0, 2 |
| ; RV32-NEXT: and t0, t0, s0 |
| ; RV32-NEXT: and s1, s1, s0 |
| ; RV32-NEXT: add t0, t0, s1 |
| ; RV32-NEXT: srli s1, t0, 4 |
| ; RV32-NEXT: add t0, t0, s1 |
| ; RV32-NEXT: and t0, t0, t6 |
| ; RV32-NEXT: slli s1, t0, 8 |
| ; RV32-NEXT: add t0, t0, s1 |
| ; RV32-NEXT: slli s1, t0, 16 |
| ; RV32-NEXT: add t0, t0, s1 |
| ; RV32-NEXT: srli t0, t0, 24 |
| ; RV32-NEXT: .LBB1_12: # %itofp-if-end |
| ; RV32-NEXT: srli s1, a5, 8 |
| ; RV32-NEXT: slli s4, a4, 24 |
| ; RV32-NEXT: or s1, s4, s1 |
| ; RV32-NEXT: slli s4, a5, 24 |
| ; RV32-NEXT: srli s5, a6, 8 |
| ; RV32-NEXT: sub s3, s3, s2 |
| ; RV32-NEXT: or s2, s5, s4 |
| ; RV32-NEXT: bnez s1, .LBB1_14 |
| ; RV32-NEXT: # %bb.13: # %itofp-if-end |
| ; RV32-NEXT: srli s4, s2, 1 |
| ; RV32-NEXT: or s4, s2, s4 |
| ; RV32-NEXT: srli s5, s4, 2 |
| ; RV32-NEXT: or s4, s4, s5 |
| ; RV32-NEXT: srli s5, s4, 4 |
| ; RV32-NEXT: or s4, s4, s5 |
| ; RV32-NEXT: srli s5, s4, 8 |
| ; RV32-NEXT: or s4, s4, s5 |
| ; RV32-NEXT: srli s5, s4, 16 |
| ; RV32-NEXT: or s4, s4, s5 |
| ; RV32-NEXT: not s4, s4 |
| ; RV32-NEXT: srli s5, s4, 1 |
| ; RV32-NEXT: and s5, s5, t5 |
| ; RV32-NEXT: sub s4, s4, s5 |
| ; RV32-NEXT: srli s5, s4, 2 |
| ; RV32-NEXT: and s4, s4, s0 |
| ; RV32-NEXT: and s5, s5, s0 |
| ; RV32-NEXT: add s4, s4, s5 |
| ; RV32-NEXT: srli s5, s4, 4 |
| ; RV32-NEXT: add s4, s4, s5 |
| ; RV32-NEXT: and s4, s4, t6 |
| ; RV32-NEXT: slli s5, s4, 8 |
| ; RV32-NEXT: add s4, s4, s5 |
| ; RV32-NEXT: slli s5, s4, 16 |
| ; RV32-NEXT: add s4, s4, s5 |
| ; RV32-NEXT: srli s4, s4, 24 |
| ; RV32-NEXT: addi s4, s4, 32 |
| ; RV32-NEXT: j .LBB1_15 |
| ; RV32-NEXT: .LBB1_14: |
| ; RV32-NEXT: srli s4, s1, 1 |
| ; RV32-NEXT: or s4, s1, s4 |
| ; RV32-NEXT: srli s5, s4, 2 |
| ; RV32-NEXT: or s4, s4, s5 |
| ; RV32-NEXT: srli s5, s4, 4 |
| ; RV32-NEXT: or s4, s4, s5 |
| ; RV32-NEXT: srli s5, s4, 8 |
| ; RV32-NEXT: or s4, s4, s5 |
| ; RV32-NEXT: srli s5, s4, 16 |
| ; RV32-NEXT: or s4, s4, s5 |
| ; RV32-NEXT: not s4, s4 |
| ; RV32-NEXT: srli s5, s4, 1 |
| ; RV32-NEXT: and s5, s5, t5 |
| ; RV32-NEXT: sub s4, s4, s5 |
| ; RV32-NEXT: srli s5, s4, 2 |
| ; RV32-NEXT: and s4, s4, s0 |
| ; RV32-NEXT: and s5, s5, s0 |
| ; RV32-NEXT: add s4, s4, s5 |
| ; RV32-NEXT: srli s5, s4, 4 |
| ; RV32-NEXT: add s4, s4, s5 |
| ; RV32-NEXT: and s4, s4, t6 |
| ; RV32-NEXT: slli s5, s4, 8 |
| ; RV32-NEXT: add s4, s4, s5 |
| ; RV32-NEXT: slli s5, s4, 16 |
| ; RV32-NEXT: add s4, s4, s5 |
| ; RV32-NEXT: srli s4, s4, 24 |
| ; RV32-NEXT: .LBB1_15: # %itofp-if-end |
| ; RV32-NEXT: or s5, t1, t2 |
| ; RV32-NEXT: sub t3, s3, t3 |
| ; RV32-NEXT: sub t4, t4, a0 |
| ; RV32-NEXT: bnez s5, .LBB1_17 |
| ; RV32-NEXT: # %bb.16: # %itofp-if-end |
| ; RV32-NEXT: addi t0, s4, 64 |
| ; RV32-NEXT: .LBB1_17: # %itofp-if-end |
| ; RV32-NEXT: srli s4, t4, 8 |
| ; RV32-NEXT: srli s3, t3, 8 |
| ; RV32-NEXT: slli s5, a6, 24 |
| ; RV32-NEXT: or s3, s5, s3 |
| ; RV32-NEXT: slli s5, t3, 24 |
| ; RV32-NEXT: or s4, s4, s5 |
| ; RV32-NEXT: bnez s3, .LBB1_20 |
| ; RV32-NEXT: # %bb.18: # %itofp-if-end |
| ; RV32-NEXT: srli s5, s4, 1 |
| ; RV32-NEXT: or s5, s4, s5 |
| ; RV32-NEXT: srli s6, s5, 2 |
| ; RV32-NEXT: or s5, s5, s6 |
| ; RV32-NEXT: srli s6, s5, 4 |
| ; RV32-NEXT: or s5, s5, s6 |
| ; RV32-NEXT: srli s6, s5, 8 |
| ; RV32-NEXT: or s5, s5, s6 |
| ; RV32-NEXT: srli s6, s5, 16 |
| ; RV32-NEXT: or s5, s5, s6 |
| ; RV32-NEXT: not s5, s5 |
| ; RV32-NEXT: srli s6, s5, 1 |
| ; RV32-NEXT: and s6, s6, t5 |
| ; RV32-NEXT: sub s5, s5, s6 |
| ; RV32-NEXT: srli s6, s5, 2 |
| ; RV32-NEXT: and s5, s5, s0 |
| ; RV32-NEXT: and s6, s6, s0 |
| ; RV32-NEXT: add s5, s5, s6 |
| ; RV32-NEXT: srli s6, s5, 4 |
| ; RV32-NEXT: add s5, s5, s6 |
| ; RV32-NEXT: and s5, s5, t6 |
| ; RV32-NEXT: slli s6, s5, 8 |
| ; RV32-NEXT: add s5, s5, s6 |
| ; RV32-NEXT: slli s6, s5, 16 |
| ; RV32-NEXT: add s5, s5, s6 |
| ; RV32-NEXT: srli s5, s5, 24 |
| ; RV32-NEXT: addi s5, s5, 32 |
| ; RV32-NEXT: slli s6, t4, 24 |
| ; RV32-NEXT: beqz s6, .LBB1_21 |
| ; RV32-NEXT: .LBB1_19: |
| ; RV32-NEXT: srli s7, s6, 1 |
| ; RV32-NEXT: or s6, s6, s7 |
| ; RV32-NEXT: srli s7, s6, 2 |
| ; RV32-NEXT: or s6, s6, s7 |
| ; RV32-NEXT: srli s7, s6, 4 |
| ; RV32-NEXT: or s6, s6, s7 |
| ; RV32-NEXT: srli s7, s6, 8 |
| ; RV32-NEXT: or s6, s6, s7 |
| ; RV32-NEXT: srli s7, s6, 16 |
| ; RV32-NEXT: or s6, s6, s7 |
| ; RV32-NEXT: not s6, s6 |
| ; RV32-NEXT: srli s7, s6, 1 |
| ; RV32-NEXT: and t5, s7, t5 |
| ; RV32-NEXT: sub t5, s6, t5 |
| ; RV32-NEXT: srli s6, t5, 2 |
| ; RV32-NEXT: and t5, t5, s0 |
| ; RV32-NEXT: and s0, s6, s0 |
| ; RV32-NEXT: add t5, t5, s0 |
| ; RV32-NEXT: srli s0, t5, 4 |
| ; RV32-NEXT: add t5, t5, s0 |
| ; RV32-NEXT: and t5, t5, t6 |
| ; RV32-NEXT: slli t6, t5, 8 |
| ; RV32-NEXT: add t5, t5, t6 |
| ; RV32-NEXT: slli t6, t5, 16 |
| ; RV32-NEXT: add t5, t5, t6 |
| ; RV32-NEXT: srli t5, t5, 24 |
| ; RV32-NEXT: or t6, s4, s3 |
| ; RV32-NEXT: beqz t6, .LBB1_22 |
| ; RV32-NEXT: j .LBB1_23 |
| ; RV32-NEXT: .LBB1_20: |
| ; RV32-NEXT: srli s5, s3, 1 |
| ; RV32-NEXT: or s5, s3, s5 |
| ; RV32-NEXT: srli s6, s5, 2 |
| ; RV32-NEXT: or s5, s5, s6 |
| ; RV32-NEXT: srli s6, s5, 4 |
| ; RV32-NEXT: or s5, s5, s6 |
| ; RV32-NEXT: srli s6, s5, 8 |
| ; RV32-NEXT: or s5, s5, s6 |
| ; RV32-NEXT: srli s6, s5, 16 |
| ; RV32-NEXT: or s5, s5, s6 |
| ; RV32-NEXT: not s5, s5 |
| ; RV32-NEXT: srli s6, s5, 1 |
| ; RV32-NEXT: and s6, s6, t5 |
| ; RV32-NEXT: sub s5, s5, s6 |
| ; RV32-NEXT: srli s6, s5, 2 |
| ; RV32-NEXT: and s5, s5, s0 |
| ; RV32-NEXT: and s6, s6, s0 |
| ; RV32-NEXT: add s5, s5, s6 |
| ; RV32-NEXT: srli s6, s5, 4 |
| ; RV32-NEXT: add s5, s5, s6 |
| ; RV32-NEXT: and s5, s5, t6 |
| ; RV32-NEXT: slli s6, s5, 8 |
| ; RV32-NEXT: add s5, s5, s6 |
| ; RV32-NEXT: slli s6, s5, 16 |
| ; RV32-NEXT: add s5, s5, s6 |
| ; RV32-NEXT: srli s5, s5, 24 |
| ; RV32-NEXT: slli s6, t4, 24 |
| ; RV32-NEXT: bnez s6, .LBB1_19 |
| ; RV32-NEXT: .LBB1_21: # %itofp-if-end |
| ; RV32-NEXT: li t5, 64 |
| ; RV32-NEXT: or t6, s4, s3 |
| ; RV32-NEXT: bnez t6, .LBB1_23 |
| ; RV32-NEXT: .LBB1_22: # %itofp-if-end |
| ; RV32-NEXT: addi s5, t5, 64 |
| ; RV32-NEXT: .LBB1_23: # %itofp-if-end |
| ; RV32-NEXT: or t2, s1, t2 |
| ; RV32-NEXT: or t1, s2, t1 |
| ; RV32-NEXT: or t1, t1, t2 |
| ; RV32-NEXT: bnez t1, .LBB1_25 |
| ; RV32-NEXT: # %bb.24: # %itofp-if-end |
| ; RV32-NEXT: addi t0, s5, 128 |
| ; RV32-NEXT: .LBB1_25: # %itofp-if-end |
| ; RV32-NEXT: li t1, 200 |
| ; RV32-NEXT: sub t2, t1, t0 |
| ; RV32-NEXT: li t1, 199 |
| ; RV32-NEXT: li t5, 25 |
| ; RV32-NEXT: sub t1, t1, t0 |
| ; RV32-NEXT: blt t2, t5, .LBB1_38 |
| ; RV32-NEXT: # %bb.26: # %itofp-if-then4 |
| ; RV32-NEXT: li t5, 26 |
| ; RV32-NEXT: beq t2, t5, .LBB1_29 |
| ; RV32-NEXT: # %bb.27: # %itofp-if-then4 |
| ; RV32-NEXT: li t5, 25 |
| ; RV32-NEXT: beq t2, t5, .LBB1_40 |
| ; RV32-NEXT: # %bb.28: # %itofp-sw-default |
| ; RV32-NEXT: li t5, 174 |
| ; RV32-NEXT: zext.b t6, a7 |
| ; RV32-NEXT: sub a7, t5, t0 |
| ; RV32-NEXT: sw zero, 112(sp) |
| ; RV32-NEXT: sw zero, 116(sp) |
| ; RV32-NEXT: sw zero, 120(sp) |
| ; RV32-NEXT: sw zero, 124(sp) |
| ; RV32-NEXT: sw zero, 96(sp) |
| ; RV32-NEXT: sw zero, 100(sp) |
| ; RV32-NEXT: sw zero, 104(sp) |
| ; RV32-NEXT: sw zero, 108(sp) |
| ; RV32-NEXT: srli t5, a7, 3 |
| ; RV32-NEXT: sw a4, 80(sp) |
| ; RV32-NEXT: sw a3, 84(sp) |
| ; RV32-NEXT: sw t6, 88(sp) |
| ; RV32-NEXT: sw zero, 92(sp) |
| ; RV32-NEXT: andi t5, t5, 28 |
| ; RV32-NEXT: addi s0, sp, 64 |
| ; RV32-NEXT: sw t4, 64(sp) |
| ; RV32-NEXT: sw t3, 68(sp) |
| ; RV32-NEXT: sw a6, 72(sp) |
| ; RV32-NEXT: sw a5, 76(sp) |
| ; RV32-NEXT: add t5, s0, t5 |
| ; RV32-NEXT: lw s0, 4(t5) |
| ; RV32-NEXT: lw s1, 8(t5) |
| ; RV32-NEXT: andi s2, a7, 31 |
| ; RV32-NEXT: lw s3, 0(t5) |
| ; RV32-NEXT: xori t5, s2, 31 |
| ; RV32-NEXT: srl s2, s0, a7 |
| ; RV32-NEXT: slli s1, s1, 1 |
| ; RV32-NEXT: addi t0, t0, 26 |
| ; RV32-NEXT: sw zero, 16(sp) |
| ; RV32-NEXT: sw zero, 20(sp) |
| ; RV32-NEXT: sw zero, 24(sp) |
| ; RV32-NEXT: sw zero, 28(sp) |
| ; RV32-NEXT: sw zero, 0(sp) |
| ; RV32-NEXT: sw zero, 4(sp) |
| ; RV32-NEXT: sw zero, 8(sp) |
| ; RV32-NEXT: sw zero, 12(sp) |
| ; RV32-NEXT: sw t4, 32(sp) |
| ; RV32-NEXT: sw t3, 36(sp) |
| ; RV32-NEXT: sw a6, 40(sp) |
| ; RV32-NEXT: sw a5, 44(sp) |
| ; RV32-NEXT: srli a5, t0, 3 |
| ; RV32-NEXT: andi a5, a5, 28 |
| ; RV32-NEXT: addi a6, sp, 32 |
| ; RV32-NEXT: sw a4, 48(sp) |
| ; RV32-NEXT: sw a3, 52(sp) |
| ; RV32-NEXT: sw t6, 56(sp) |
| ; RV32-NEXT: sub a3, a6, a5 |
| ; RV32-NEXT: sll a4, s1, t5 |
| ; RV32-NEXT: lw a5, 16(a3) |
| ; RV32-NEXT: lw a6, 20(a3) |
| ; RV32-NEXT: lw t3, 4(a3) |
| ; RV32-NEXT: lw t4, 0(a3) |
| ; RV32-NEXT: lw t6, 12(a3) |
| ; RV32-NEXT: lw s1, 8(a3) |
| ; RV32-NEXT: or a4, s2, a4 |
| ; RV32-NEXT: srl a7, s3, a7 |
| ; RV32-NEXT: slli s0, s0, 1 |
| ; RV32-NEXT: lw a3, 24(a3) |
| ; RV32-NEXT: or s2, t3, a6 |
| ; RV32-NEXT: or s2, s2, t6 |
| ; RV32-NEXT: or a5, a5, t4 |
| ; RV32-NEXT: or t4, a5, s1 |
| ; RV32-NEXT: andi s3, t0, 31 |
| ; RV32-NEXT: srli t4, t4, 1 |
| ; RV32-NEXT: xori s3, s3, 31 |
| ; RV32-NEXT: sll s2, s2, t0 |
| ; RV32-NEXT: srl t4, t4, s3 |
| ; RV32-NEXT: sll s1, s1, t0 |
| ; RV32-NEXT: srli t3, t3, 1 |
| ; RV32-NEXT: srl t3, t3, s3 |
| ; RV32-NEXT: srli a6, a6, 1 |
| ; RV32-NEXT: sll a3, a3, t0 |
| ; RV32-NEXT: srl a6, a6, s3 |
| ; RV32-NEXT: or t3, s1, t3 |
| ; RV32-NEXT: or a3, a3, a6 |
| ; RV32-NEXT: zext.b a3, a3 |
| ; RV32-NEXT: srli a6, t6, 1 |
| ; RV32-NEXT: sll a5, a5, t0 |
| ; RV32-NEXT: srl a6, a6, s3 |
| ; RV32-NEXT: or a3, t3, a3 |
| ; RV32-NEXT: or a5, a5, a6 |
| ; RV32-NEXT: or a6, t4, s2 |
| ; RV32-NEXT: or a3, a5, a3 |
| ; RV32-NEXT: sll a5, s0, t5 |
| ; RV32-NEXT: or a3, a3, a6 |
| ; RV32-NEXT: or a5, a7, a5 |
| ; RV32-NEXT: snez a3, a3 |
| ; RV32-NEXT: or t4, a5, a3 |
| ; RV32-NEXT: mv t3, a4 |
| ; RV32-NEXT: .LBB1_29: # %itofp-sw-epilog |
| ; RV32-NEXT: slli a3, t4, 29 |
| ; RV32-NEXT: srli a3, a3, 31 |
| ; RV32-NEXT: or a3, t4, a3 |
| ; RV32-NEXT: addi a3, a3, 1 |
| ; RV32-NEXT: seqz a4, a3 |
| ; RV32-NEXT: slli a5, a3, 5 |
| ; RV32-NEXT: add t3, t3, a4 |
| ; RV32-NEXT: bltz a5, .LBB1_39 |
| ; RV32-NEXT: # %bb.30: |
| ; RV32-NEXT: srli a3, a3, 2 |
| ; RV32-NEXT: slli t3, t3, 30 |
| ; RV32-NEXT: or a3, a3, t3 |
| ; RV32-NEXT: .LBB1_31: # %itofp-if-end26 |
| ; RV32-NEXT: mv t2, t1 |
| ; RV32-NEXT: .LBB1_32: # %itofp-if-end26 |
| ; RV32-NEXT: lui a4, 1046528 |
| ; RV32-NEXT: lw s0, 220(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s1, 216(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s2, 212(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s3, 208(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s4, 204(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s5, 200(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s6, 196(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s7, 192(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: addi sp, sp, 224 |
| ; RV32-NEXT: bgez a2, .LBB1_35 |
| ; RV32-NEXT: # %bb.33: # %itofp-if-end26 |
| ; RV32-NEXT: li a2, 127 |
| ; RV32-NEXT: bgeu a2, t1, .LBB1_36 |
| ; RV32-NEXT: .LBB1_34: # %itofp-return |
| ; RV32-NEXT: sw a4, 0(a1) |
| ; RV32-NEXT: ret |
| ; RV32-NEXT: .LBB1_35: # %itofp-if-end26 |
| ; RV32-NEXT: lui a4, 522240 |
| ; RV32-NEXT: li a2, 127 |
| ; RV32-NEXT: bltu a2, t1, .LBB1_34 |
| ; RV32-NEXT: .LBB1_36: # %itofp-if-end26 |
| ; RV32-NEXT: lui a2, 524288 |
| ; RV32-NEXT: slli a3, a3, 9 |
| ; RV32-NEXT: slli t2, t2, 23 |
| ; RV32-NEXT: and a0, a0, a2 |
| ; RV32-NEXT: lui a2, 260096 |
| ; RV32-NEXT: srli a3, a3, 9 |
| ; RV32-NEXT: add a2, t2, a2 |
| ; RV32-NEXT: or a0, a3, a0 |
| ; RV32-NEXT: or a4, a0, a2 |
| ; RV32-NEXT: sw a4, 0(a1) |
| ; RV32-NEXT: ret |
| ; RV32-NEXT: .LBB1_37: |
| ; RV32-NEXT: sw zero, 0(a1) |
| ; RV32-NEXT: ret |
| ; RV32-NEXT: .LBB1_38: # %itofp-if-else |
| ; RV32-NEXT: addi a3, t0, -176 |
| ; RV32-NEXT: sw t4, 160(sp) |
| ; RV32-NEXT: srli a4, a3, 3 |
| ; RV32-NEXT: sw zero, 144(sp) |
| ; RV32-NEXT: sw zero, 148(sp) |
| ; RV32-NEXT: sw zero, 152(sp) |
| ; RV32-NEXT: sw zero, 156(sp) |
| ; RV32-NEXT: andi a4, a4, 28 |
| ; RV32-NEXT: addi a5, sp, 160 |
| ; RV32-NEXT: sw zero, 128(sp) |
| ; RV32-NEXT: sw zero, 132(sp) |
| ; RV32-NEXT: sw zero, 136(sp) |
| ; RV32-NEXT: sw zero, 140(sp) |
| ; RV32-NEXT: sub a5, a5, a4 |
| ; RV32-NEXT: lw a4, 0(a5) |
| ; RV32-NEXT: sll a3, a4, a3 |
| ; RV32-NEXT: j .LBB1_31 |
| ; RV32-NEXT: .LBB1_39: # %itofp-if-then20 |
| ; RV32-NEXT: srli a3, a3, 3 |
| ; RV32-NEXT: slli t3, t3, 29 |
| ; RV32-NEXT: or a3, a3, t3 |
| ; RV32-NEXT: j .LBB1_32 |
| ; RV32-NEXT: .LBB1_40: # %itofp-sw-bb |
| ; RV32-NEXT: srli a3, t4, 31 |
| ; RV32-NEXT: slli t3, t3, 1 |
| ; RV32-NEXT: or t3, t3, a3 |
| ; RV32-NEXT: slli t4, t4, 1 |
| ; RV32-NEXT: j .LBB1_29 |
| %1 = load i200, ptr %in, align 8 |
| %2 = sitofp i200 %1 to float |
| store float %2, ptr %out, align 4 |
| ret void |
| } |
| |
| define void @test_float_to_bitint_200(ptr %in, ptr %out) nounwind { |
| ; RV64-LABEL: test_float_to_bitint_200: |
| ; RV64: # %bb.0: # %fp-to-i-entry |
| ; RV64-NEXT: addi sp, sp, -160 |
| ; RV64-NEXT: sd ra, 152(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s0, 144(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s1, 136(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s2, 128(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s3, 120(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s4, 112(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s5, 104(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s6, 96(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s7, 88(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s8, 80(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: sd s9, 72(sp) # 8-byte Folded Spill |
| ; RV64-NEXT: li a3, 127 |
| ; RV64-NEXT: lw a2, 0(a0) |
| ; RV64-NEXT: slli a0, a2, 33 |
| ; RV64-NEXT: srli a0, a0, 56 |
| ; RV64-NEXT: mv s0, a1 |
| ; RV64-NEXT: bgeu a0, a3, .LBB2_2 |
| ; RV64-NEXT: # %bb.1: |
| ; RV64-NEXT: li s2, 0 |
| ; RV64-NEXT: li s6, 0 |
| ; RV64-NEXT: li a0, 0 |
| ; RV64-NEXT: li a1, 0 |
| ; RV64-NEXT: j .LBB2_5 |
| ; RV64-NEXT: .LBB2_2: # %fp-to-i-if-check.exp.size |
| ; RV64-NEXT: slli a1, a2, 41 |
| ; RV64-NEXT: sraiw s1, a2, 31 |
| ; RV64-NEXT: srli a1, a1, 41 |
| ; RV64-NEXT: lui a2, 2048 |
| ; RV64-NEXT: li a3, 149 |
| ; RV64-NEXT: or a1, a1, a2 |
| ; RV64-NEXT: ori s3, s1, 1 |
| ; RV64-NEXT: bltu a3, a0, .LBB2_4 |
| ; RV64-NEXT: # %bb.3: # %fp-to-i-if-exp.small |
| ; RV64-NEXT: li a2, 150 |
| ; RV64-NEXT: sub a2, a2, a0 |
| ; RV64-NEXT: srlw s4, a1, a2 |
| ; RV64-NEXT: mv a0, s4 |
| ; RV64-NEXT: li a1, 0 |
| ; RV64-NEXT: mv a2, s3 |
| ; RV64-NEXT: li a3, 0 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: mv s2, a0 |
| ; RV64-NEXT: mv s5, a1 |
| ; RV64-NEXT: li a0, 0 |
| ; RV64-NEXT: li a1, 0 |
| ; RV64-NEXT: mv a2, s3 |
| ; RV64-NEXT: li a3, 0 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: add s5, a0, s5 |
| ; RV64-NEXT: sltu a0, s5, a0 |
| ; RV64-NEXT: add s7, a1, a0 |
| ; RV64-NEXT: mv a0, s4 |
| ; RV64-NEXT: li a1, 0 |
| ; RV64-NEXT: mv a2, s1 |
| ; RV64-NEXT: li a3, 0 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: add s6, a0, s5 |
| ; RV64-NEXT: sltu a0, s6, a0 |
| ; RV64-NEXT: add a0, a1, a0 |
| ; RV64-NEXT: add s8, s7, a0 |
| ; RV64-NEXT: li a0, 0 |
| ; RV64-NEXT: li a1, 0 |
| ; RV64-NEXT: mv a2, s1 |
| ; RV64-NEXT: li a3, 0 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: mv s3, a0 |
| ; RV64-NEXT: mv s5, a1 |
| ; RV64-NEXT: add s9, a0, s8 |
| ; RV64-NEXT: mv a0, s1 |
| ; RV64-NEXT: mv a1, s1 |
| ; RV64-NEXT: mv a2, s4 |
| ; RV64-NEXT: li a3, 0 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: sltu a2, s8, s7 |
| ; RV64-NEXT: sltu a3, s9, s3 |
| ; RV64-NEXT: add a2, s5, a2 |
| ; RV64-NEXT: add a0, s9, a0 |
| ; RV64-NEXT: add a2, a2, a3 |
| ; RV64-NEXT: sltu a3, a0, s9 |
| ; RV64-NEXT: add a1, a2, a1 |
| ; RV64-NEXT: add a1, a1, a3 |
| ; RV64-NEXT: j .LBB2_5 |
| ; RV64-NEXT: .LBB2_4: # %fp-to-i-if-exp.large |
| ; RV64-NEXT: addi a0, a0, -150 |
| ; RV64-NEXT: srli a2, a0, 3 |
| ; RV64-NEXT: sd a1, 32(sp) |
| ; RV64-NEXT: sd zero, 40(sp) |
| ; RV64-NEXT: sd zero, 48(sp) |
| ; RV64-NEXT: sd zero, 56(sp) |
| ; RV64-NEXT: andi a2, a2, 24 |
| ; RV64-NEXT: addi a1, sp, 32 |
| ; RV64-NEXT: sd zero, 0(sp) |
| ; RV64-NEXT: sd zero, 8(sp) |
| ; RV64-NEXT: sd zero, 16(sp) |
| ; RV64-NEXT: sd zero, 24(sp) |
| ; RV64-NEXT: sub a1, a1, a2 |
| ; RV64-NEXT: ld a4, 0(a1) |
| ; RV64-NEXT: ld a2, 8(a1) |
| ; RV64-NEXT: andi a3, a0, 63 |
| ; RV64-NEXT: ld a5, 16(a1) |
| ; RV64-NEXT: ld a1, 24(a1) |
| ; RV64-NEXT: srli a6, a4, 1 |
| ; RV64-NEXT: xori a3, a3, 63 |
| ; RV64-NEXT: sll a7, a2, a0 |
| ; RV64-NEXT: srl a6, a6, a3 |
| ; RV64-NEXT: or s4, a7, a6 |
| ; RV64-NEXT: srli a2, a2, 1 |
| ; RV64-NEXT: sll a6, a5, a0 |
| ; RV64-NEXT: srl a2, a2, a3 |
| ; RV64-NEXT: or a2, a6, a2 |
| ; RV64-NEXT: srli a5, a5, 1 |
| ; RV64-NEXT: sll a1, a1, a0 |
| ; RV64-NEXT: srl a3, a5, a3 |
| ; RV64-NEXT: or a3, a1, a3 |
| ; RV64-NEXT: sll s5, a4, a0 |
| ; RV64-NEXT: mv a0, s3 |
| ; RV64-NEXT: mv a1, s1 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: mv s2, a0 |
| ; RV64-NEXT: mv s6, a1 |
| ; RV64-NEXT: mv a0, s1 |
| ; RV64-NEXT: mv a1, s1 |
| ; RV64-NEXT: mv a2, s5 |
| ; RV64-NEXT: mv a3, s4 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: add s8, a0, s2 |
| ; RV64-NEXT: add a1, a1, s6 |
| ; RV64-NEXT: sltu a0, s8, a0 |
| ; RV64-NEXT: add s9, a1, a0 |
| ; RV64-NEXT: mv a0, s4 |
| ; RV64-NEXT: li a1, 0 |
| ; RV64-NEXT: mv a2, s3 |
| ; RV64-NEXT: li a3, 0 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: mv s6, a0 |
| ; RV64-NEXT: mv s7, a1 |
| ; RV64-NEXT: mv a0, s5 |
| ; RV64-NEXT: li a1, 0 |
| ; RV64-NEXT: mv a2, s3 |
| ; RV64-NEXT: li a3, 0 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: mv s2, a0 |
| ; RV64-NEXT: add s3, s6, a1 |
| ; RV64-NEXT: sltu a0, s3, s6 |
| ; RV64-NEXT: add s7, s7, a0 |
| ; RV64-NEXT: mv a0, s5 |
| ; RV64-NEXT: li a1, 0 |
| ; RV64-NEXT: mv a2, s1 |
| ; RV64-NEXT: li a3, 0 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: add s6, a0, s3 |
| ; RV64-NEXT: sltu a0, s6, a0 |
| ; RV64-NEXT: add a0, a1, a0 |
| ; RV64-NEXT: add s3, s7, a0 |
| ; RV64-NEXT: sltu s5, s3, s7 |
| ; RV64-NEXT: mv a0, s4 |
| ; RV64-NEXT: li a1, 0 |
| ; RV64-NEXT: mv a2, s1 |
| ; RV64-NEXT: li a3, 0 |
| ; RV64-NEXT: call __multi3 |
| ; RV64-NEXT: add s3, a0, s3 |
| ; RV64-NEXT: add a1, a1, s5 |
| ; RV64-NEXT: sltu a0, s3, a0 |
| ; RV64-NEXT: add a1, a1, a0 |
| ; RV64-NEXT: add a0, s3, s8 |
| ; RV64-NEXT: add a1, a1, s9 |
| ; RV64-NEXT: sltu a2, a0, s3 |
| ; RV64-NEXT: add a1, a1, a2 |
| ; RV64-NEXT: .LBB2_5: # %fp-to-i-cleanup |
| ; RV64-NEXT: sd s2, 0(s0) |
| ; RV64-NEXT: sd s6, 8(s0) |
| ; RV64-NEXT: sd a0, 16(s0) |
| ; RV64-NEXT: sb a1, 24(s0) |
| ; RV64-NEXT: ld ra, 152(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s0, 144(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s1, 136(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s2, 128(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s3, 120(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s4, 112(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s5, 104(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s6, 96(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s7, 88(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s8, 80(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: ld s9, 72(sp) # 8-byte Folded Reload |
| ; RV64-NEXT: addi sp, sp, 160 |
| ; RV64-NEXT: ret |
| ; |
| ; RV32-LABEL: test_float_to_bitint_200: |
| ; RV32: # %bb.0: # %fp-to-i-entry |
| ; RV32-NEXT: addi sp, sp, -256 |
| ; RV32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s1, 244(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s2, 240(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s3, 236(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s4, 232(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s5, 228(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s6, 224(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s7, 220(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s8, 216(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s9, 212(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s10, 208(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s11, 204(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: li a3, 127 |
| ; RV32-NEXT: lw a2, 0(a0) |
| ; RV32-NEXT: slli a0, a2, 1 |
| ; RV32-NEXT: srli a0, a0, 24 |
| ; RV32-NEXT: mv s0, a1 |
| ; RV32-NEXT: bgeu a0, a3, .LBB2_2 |
| ; RV32-NEXT: # %bb.1: |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: li a2, 0 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: li a4, 0 |
| ; RV32-NEXT: li s10, 0 |
| ; RV32-NEXT: li s11, 0 |
| ; RV32-NEXT: li a0, 0 |
| ; RV32-NEXT: j .LBB2_22 |
| ; RV32-NEXT: .LBB2_2: # %fp-to-i-if-check.exp.size |
| ; RV32-NEXT: srai s1, a2, 31 |
| ; RV32-NEXT: slli a2, a2, 9 |
| ; RV32-NEXT: zext.b a1, s1 |
| ; RV32-NEXT: sw a1, 120(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: srli a2, a2, 9 |
| ; RV32-NEXT: lui a1, 2048 |
| ; RV32-NEXT: li a3, 149 |
| ; RV32-NEXT: or a1, a2, a1 |
| ; RV32-NEXT: ori s10, s1, 1 |
| ; RV32-NEXT: bltu a3, a0, .LBB2_8 |
| ; RV32-NEXT: # %bb.3: # %fp-to-i-if-exp.small |
| ; RV32-NEXT: li a2, 150 |
| ; RV32-NEXT: sub a2, a2, a0 |
| ; RV32-NEXT: srl s5, a1, a2 |
| ; RV32-NEXT: mv a0, s5 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s10 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: sw a0, 116(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: mv s2, a1 |
| ; RV32-NEXT: li a0, 0 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s10 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add s2, a0, s2 |
| ; RV32-NEXT: sltu a0, s2, a0 |
| ; RV32-NEXT: add s3, a1, a0 |
| ; RV32-NEXT: mv a0, s5 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add s2, a0, s2 |
| ; RV32-NEXT: sw s2, 112(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sltu a0, s2, a0 |
| ; RV32-NEXT: add a0, a1, a0 |
| ; RV32-NEXT: add s2, s3, a0 |
| ; RV32-NEXT: li a0, 0 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add s7, a0, s2 |
| ; RV32-NEXT: sltu a2, s2, s3 |
| ; RV32-NEXT: sltu a0, s7, a0 |
| ; RV32-NEXT: add a1, a1, a2 |
| ; RV32-NEXT: add s8, a1, a0 |
| ; RV32-NEXT: mv a0, s5 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s4, a0 |
| ; RV32-NEXT: mv s6, a1 |
| ; RV32-NEXT: li a0, 0 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s3, a0 |
| ; RV32-NEXT: mv s2, a1 |
| ; RV32-NEXT: add s6, a0, s6 |
| ; RV32-NEXT: mv a0, s5 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add s7, s4, s7 |
| ; RV32-NEXT: add a2, a0, s6 |
| ; RV32-NEXT: add s8, a2, s8 |
| ; RV32-NEXT: sw s7, 108(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sltu s4, s7, s4 |
| ; RV32-NEXT: add s8, s8, s4 |
| ; RV32-NEXT: beq s8, a2, .LBB2_5 |
| ; RV32-NEXT: # %bb.4: # %fp-to-i-if-exp.small |
| ; RV32-NEXT: sltu s4, s8, a2 |
| ; RV32-NEXT: .LBB2_5: # %fp-to-i-if-exp.small |
| ; RV32-NEXT: sw s8, 104(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sltu a3, s6, s3 |
| ; RV32-NEXT: sltu a0, a2, a0 |
| ; RV32-NEXT: add s6, s2, a3 |
| ; RV32-NEXT: add a0, a1, a0 |
| ; RV32-NEXT: add s7, s6, a0 |
| ; RV32-NEXT: li a0, 0 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s2, a0 |
| ; RV32-NEXT: mv s3, a1 |
| ; RV32-NEXT: add s8, a0, s7 |
| ; RV32-NEXT: add s9, s8, s4 |
| ; RV32-NEXT: mv a0, s1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s5 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s4, a1 |
| ; RV32-NEXT: sltu a1, s7, s6 |
| ; RV32-NEXT: add s10, s9, a0 |
| ; RV32-NEXT: sltu a0, s8, s2 |
| ; RV32-NEXT: add a1, s3, a1 |
| ; RV32-NEXT: sltu s8, s9, s8 |
| ; RV32-NEXT: add a0, a1, a0 |
| ; RV32-NEXT: sltu s6, s10, s9 |
| ; RV32-NEXT: add s8, a0, s8 |
| ; RV32-NEXT: mv a0, s1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s5 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s3, a0 |
| ; RV32-NEXT: mv s2, a1 |
| ; RV32-NEXT: add s4, a0, s4 |
| ; RV32-NEXT: mv a0, s1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: li a2, 0 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add a2, a0, s4 |
| ; RV32-NEXT: add s11, s8, a2 |
| ; RV32-NEXT: add s11, s11, s6 |
| ; RV32-NEXT: beq s11, s8, .LBB2_7 |
| ; RV32-NEXT: # %bb.6: # %fp-to-i-if-exp.small |
| ; RV32-NEXT: sltu s6, s11, s8 |
| ; RV32-NEXT: .LBB2_7: # %fp-to-i-if-exp.small |
| ; RV32-NEXT: sltu a3, s4, s3 |
| ; RV32-NEXT: sltu a0, a2, a0 |
| ; RV32-NEXT: add a3, s2, a3 |
| ; RV32-NEXT: add a0, a1, a0 |
| ; RV32-NEXT: add s2, a3, a0 |
| ; RV32-NEXT: mv a0, s1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: li a2, 0 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s1, a0 |
| ; RV32-NEXT: mv a0, s5 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: lw a2, 120(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: # implicit-def: $x13 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add a0, s1, a0 |
| ; RV32-NEXT: add a0, a0, s6 |
| ; RV32-NEXT: add a0, a0, s2 |
| ; RV32-NEXT: j .LBB2_21 |
| ; RV32-NEXT: .LBB2_8: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: addi a7, a0, -150 |
| ; RV32-NEXT: sw zero, 184(sp) |
| ; RV32-NEXT: sw zero, 188(sp) |
| ; RV32-NEXT: sw zero, 192(sp) |
| ; RV32-NEXT: sw zero, 196(sp) |
| ; RV32-NEXT: sw a1, 168(sp) |
| ; RV32-NEXT: sw zero, 172(sp) |
| ; RV32-NEXT: sw zero, 176(sp) |
| ; RV32-NEXT: sw zero, 180(sp) |
| ; RV32-NEXT: srli a0, a7, 3 |
| ; RV32-NEXT: sw zero, 152(sp) |
| ; RV32-NEXT: sw zero, 156(sp) |
| ; RV32-NEXT: sw zero, 160(sp) |
| ; RV32-NEXT: sw zero, 164(sp) |
| ; RV32-NEXT: andi a0, a0, 28 |
| ; RV32-NEXT: addi a1, sp, 168 |
| ; RV32-NEXT: sw zero, 136(sp) |
| ; RV32-NEXT: sw zero, 140(sp) |
| ; RV32-NEXT: sw zero, 144(sp) |
| ; RV32-NEXT: sw zero, 148(sp) |
| ; RV32-NEXT: sub a1, a1, a0 |
| ; RV32-NEXT: lw a0, 16(a1) |
| ; RV32-NEXT: lw t0, 20(a1) |
| ; RV32-NEXT: andi a2, a7, 31 |
| ; RV32-NEXT: lw a3, 0(a1) |
| ; RV32-NEXT: lw a4, 4(a1) |
| ; RV32-NEXT: lw a5, 8(a1) |
| ; RV32-NEXT: lw a6, 12(a1) |
| ; RV32-NEXT: xori a2, a2, 31 |
| ; RV32-NEXT: lw t1, 24(a1) |
| ; RV32-NEXT: sw t1, 64(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: lw a1, 28(a1) |
| ; RV32-NEXT: sw a1, 68(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: srli a1, a0, 1 |
| ; RV32-NEXT: sw t0, 76(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sll t0, t0, a7 |
| ; RV32-NEXT: sw t0, 100(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: srl s7, a1, a2 |
| ; RV32-NEXT: sll a0, a0, a7 |
| ; RV32-NEXT: sw a0, 108(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: srli a0, a6, 1 |
| ; RV32-NEXT: srl a0, a0, a2 |
| ; RV32-NEXT: sw a0, 104(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: srli a0, a5, 1 |
| ; RV32-NEXT: sll a1, a6, a7 |
| ; RV32-NEXT: srl a0, a0, a2 |
| ; RV32-NEXT: or s8, a1, a0 |
| ; RV32-NEXT: srli a0, a4, 1 |
| ; RV32-NEXT: sll a1, a5, a7 |
| ; RV32-NEXT: srl a0, a0, a2 |
| ; RV32-NEXT: or s9, a1, a0 |
| ; RV32-NEXT: srli a0, a3, 1 |
| ; RV32-NEXT: sll a1, a4, a7 |
| ; RV32-NEXT: sw a2, 72(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: srl a0, a0, a2 |
| ; RV32-NEXT: or s5, a1, a0 |
| ; RV32-NEXT: sw a7, 80(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sll s6, a3, a7 |
| ; RV32-NEXT: mv a0, s5 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s10 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s2, a0 |
| ; RV32-NEXT: mv s3, a1 |
| ; RV32-NEXT: mv a0, s6 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s10 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: sw a0, 116(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s4, s2, a1 |
| ; RV32-NEXT: sltu a0, s4, s2 |
| ; RV32-NEXT: add s3, s3, a0 |
| ; RV32-NEXT: sw s6, 124(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: mv a0, s6 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add s4, a0, s4 |
| ; RV32-NEXT: sw s4, 112(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sltu a0, s4, a0 |
| ; RV32-NEXT: add a0, a1, a0 |
| ; RV32-NEXT: add s2, s3, a0 |
| ; RV32-NEXT: sltu s3, s2, s3 |
| ; RV32-NEXT: sw s5, 132(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: mv a0, s5 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add s5, a0, s2 |
| ; RV32-NEXT: add a1, a1, s3 |
| ; RV32-NEXT: sltu a0, s5, a0 |
| ; RV32-NEXT: add s11, a1, a0 |
| ; RV32-NEXT: mv a0, s9 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s10 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s4, a0 |
| ; RV32-NEXT: mv s6, a1 |
| ; RV32-NEXT: sw s8, 128(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: mv a0, s8 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s10 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s10, a0 |
| ; RV32-NEXT: mv s2, a1 |
| ; RV32-NEXT: add s3, a0, s6 |
| ; RV32-NEXT: sw s9, 96(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: mv a0, s9 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add s5, s4, s5 |
| ; RV32-NEXT: add a2, a0, s3 |
| ; RV32-NEXT: add s11, a2, s11 |
| ; RV32-NEXT: sltu s6, s5, s4 |
| ; RV32-NEXT: add s11, s11, s6 |
| ; RV32-NEXT: beq s11, a2, .LBB2_10 |
| ; RV32-NEXT: # %bb.9: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: sltu s6, s11, a2 |
| ; RV32-NEXT: .LBB2_10: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: lw a3, 100(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: or a3, a3, s7 |
| ; RV32-NEXT: sw a3, 92(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sltu a3, s3, s10 |
| ; RV32-NEXT: sltu a0, a2, a0 |
| ; RV32-NEXT: add a3, s2, a3 |
| ; RV32-NEXT: add a0, a1, a0 |
| ; RV32-NEXT: lw a1, 108(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a2, 104(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: or a1, a1, a2 |
| ; RV32-NEXT: sw a1, 100(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw a3, 88(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s2, a3, a0 |
| ; RV32-NEXT: lw a0, 128(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: sw a1, 60(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s2, 84(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw a0, 52(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s2, a0, s2 |
| ; RV32-NEXT: sw s2, 56(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s4, s2, s6 |
| ; RV32-NEXT: lw a0, 132(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s6, a0 |
| ; RV32-NEXT: mv s3, a1 |
| ; RV32-NEXT: lw s2, 124(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: mv a0, s2 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s8, a0 |
| ; RV32-NEXT: add s9, s6, a1 |
| ; RV32-NEXT: mv a0, s2 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add s5, s8, s5 |
| ; RV32-NEXT: add a2, a0, s9 |
| ; RV32-NEXT: add s11, a2, s11 |
| ; RV32-NEXT: sw s5, 108(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sltu s5, s5, s8 |
| ; RV32-NEXT: add s11, s11, s5 |
| ; RV32-NEXT: beq s11, a2, .LBB2_12 |
| ; RV32-NEXT: # %bb.11: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: sltu s5, s11, a2 |
| ; RV32-NEXT: .LBB2_12: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: sw s11, 104(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sltu a3, s9, s6 |
| ; RV32-NEXT: sltu a0, a2, a0 |
| ; RV32-NEXT: add s9, s3, a3 |
| ; RV32-NEXT: add a0, a1, a0 |
| ; RV32-NEXT: add s6, s9, a0 |
| ; RV32-NEXT: lw a0, 132(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s8, a0 |
| ; RV32-NEXT: sw a1, 40(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s3, a0, s6 |
| ; RV32-NEXT: add s2, s3, s5 |
| ; RV32-NEXT: add s7, s4, s2 |
| ; RV32-NEXT: lw s11, 96(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: mv a0, s11 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: sw a0, 48(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw a1, 36(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s5, a0, s7 |
| ; RV32-NEXT: ori a0, s1, 1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: lw a2, 100(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s10, a0 |
| ; RV32-NEXT: sw a1, 20(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: mv a0, s1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: lw a2, 124(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv a4, a0 |
| ; RV32-NEXT: sw a0, 8(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw a1, 44(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: lw a3, 56(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a0, 52(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sltu a0, a3, a0 |
| ; RV32-NEXT: add a4, a4, s10 |
| ; RV32-NEXT: sw a4, 4(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: lw a1, 88(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a2, 84(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sltu a1, a2, a1 |
| ; RV32-NEXT: add s10, s5, a4 |
| ; RV32-NEXT: lw a2, 60(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add a1, a2, a1 |
| ; RV32-NEXT: sltu a2, s4, a3 |
| ; RV32-NEXT: add a0, a0, a2 |
| ; RV32-NEXT: sltu a2, s6, s9 |
| ; RV32-NEXT: lw a3, 40(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add a2, a3, a2 |
| ; RV32-NEXT: sltu a3, s3, s8 |
| ; RV32-NEXT: sltu a4, s2, s3 |
| ; RV32-NEXT: add a2, a2, a3 |
| ; RV32-NEXT: add a0, a1, a0 |
| ; RV32-NEXT: add a2, a2, a4 |
| ; RV32-NEXT: sltu s6, s7, s4 |
| ; RV32-NEXT: mv s4, a0 |
| ; RV32-NEXT: add a2, a0, a2 |
| ; RV32-NEXT: sltu s7, s10, s5 |
| ; RV32-NEXT: sw s6, 84(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s6, a2, s6 |
| ; RV32-NEXT: lw a0, 128(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: sw a1, 40(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw a0, 32(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: lw s3, 36(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add s3, a0, s3 |
| ; RV32-NEXT: mv a0, s11 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: sw a1, 16(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw s3, 24(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw a0, 12(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s3, a0, s3 |
| ; RV32-NEXT: lw a0, 48(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sltu s5, s5, a0 |
| ; RV32-NEXT: add s2, s3, s5 |
| ; RV32-NEXT: add s2, s2, s6 |
| ; RV32-NEXT: mv a0, s1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: lw a2, 132(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s9, a0 |
| ; RV32-NEXT: sw a1, 60(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: mv a0, s1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: lw a2, 124(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: sw a1, 52(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw a0, 48(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: lw a1, 44(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add a0, a0, a1 |
| ; RV32-NEXT: sw s9, 56(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw a0, 44(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s9, s9, a0 |
| ; RV32-NEXT: mv a0, s1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: lw a2, 100(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: sw a1, 36(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw a0, 28(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: lw s8, 20(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add s8, a0, s8 |
| ; RV32-NEXT: ori a0, s1, 1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: lw a2, 92(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: lw a2, 8(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a3, 4(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sltu a2, a3, a2 |
| ; RV32-NEXT: sw s8, 20(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: sw a0, 8(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add a0, a0, s8 |
| ; RV32-NEXT: sw a0, 4(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s8, s9, a0 |
| ; RV32-NEXT: mv a6, a2 |
| ; RV32-NEXT: add s8, s8, a2 |
| ; RV32-NEXT: sw s7, 88(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: add s11, s8, s7 |
| ; RV32-NEXT: add s11, s2, s11 |
| ; RV32-NEXT: sw a1, 0(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: beq s11, s2, .LBB2_14 |
| ; RV32-NEXT: # %bb.13: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: sltu a0, s11, s2 |
| ; RV32-NEXT: sw a0, 88(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: .LBB2_14: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: lw a0, 76(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: srli a0, a0, 1 |
| ; RV32-NEXT: lw a2, 64(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: srli a1, a2, 1 |
| ; RV32-NEXT: beq s2, s3, .LBB2_16 |
| ; RV32-NEXT: # %bb.15: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: sltu s5, s2, s3 |
| ; RV32-NEXT: .LBB2_16: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: lw a4, 80(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sll a2, a2, a4 |
| ; RV32-NEXT: lw a5, 72(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: srl a3, a0, a5 |
| ; RV32-NEXT: lw a0, 68(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sll a0, a0, a4 |
| ; RV32-NEXT: srl a1, a1, a5 |
| ; RV32-NEXT: mv s7, a6 |
| ; RV32-NEXT: beq s6, s4, .LBB2_18 |
| ; RV32-NEXT: # %bb.17: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: sltu a4, s6, s4 |
| ; RV32-NEXT: sw a4, 84(sp) # 4-byte Folded Spill |
| ; RV32-NEXT: .LBB2_18: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: or s2, a2, a3 |
| ; RV32-NEXT: lw a2, 32(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a3, 24(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sltu a2, a3, a2 |
| ; RV32-NEXT: lw a3, 12(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sltu a3, s3, a3 |
| ; RV32-NEXT: lw a4, 40(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add a2, a4, a2 |
| ; RV32-NEXT: lw a4, 16(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add a3, a4, a3 |
| ; RV32-NEXT: or s3, a0, a1 |
| ; RV32-NEXT: add s4, a2, a3 |
| ; RV32-NEXT: lw a0, 128(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: lw a1, 84(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add a0, a0, a1 |
| ; RV32-NEXT: add a0, a0, s5 |
| ; RV32-NEXT: add s5, a0, s4 |
| ; RV32-NEXT: beq s8, s9, .LBB2_20 |
| ; RV32-NEXT: # %bb.19: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: sltu s7, s8, s9 |
| ; RV32-NEXT: .LBB2_20: # %fp-to-i-if-exp.large |
| ; RV32-NEXT: lw a0, 100(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s6, 92(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: mv a1, s6 |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: mv a3, s1 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s4, a0 |
| ; RV32-NEXT: mv a0, s2 |
| ; RV32-NEXT: mv a1, s3 |
| ; RV32-NEXT: ori a2, s1, 1 |
| ; RV32-NEXT: mv a3, s1 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: lw a1, 28(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a2, 20(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sltu a1, a2, a1 |
| ; RV32-NEXT: lw a2, 8(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a3, 4(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sltu a2, a3, a2 |
| ; RV32-NEXT: lw a3, 36(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add a1, a3, a1 |
| ; RV32-NEXT: lw a3, 0(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add a2, a3, a2 |
| ; RV32-NEXT: add s4, a0, s4 |
| ; RV32-NEXT: add s2, a1, a2 |
| ; RV32-NEXT: mv a0, s1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s6 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: add a0, a0, s4 |
| ; RV32-NEXT: add s3, a0, s2 |
| ; RV32-NEXT: lw a0, 96(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a1, 128(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: mv a2, s1 |
| ; RV32-NEXT: mv a3, s1 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: mv s2, a0 |
| ; RV32-NEXT: lw a0, 124(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s6, 132(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: mv a1, s6 |
| ; RV32-NEXT: lw a2, 120(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: lw a1, 56(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sltu a1, s9, a1 |
| ; RV32-NEXT: lw a2, 48(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a3, 44(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: sltu a2, a3, a2 |
| ; RV32-NEXT: lw a3, 60(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add a1, a3, a1 |
| ; RV32-NEXT: lw a3, 52(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add a2, a3, a2 |
| ; RV32-NEXT: add s2, s2, a0 |
| ; RV32-NEXT: add s4, a2, a1 |
| ; RV32-NEXT: mv a0, s1 |
| ; RV32-NEXT: li a1, 0 |
| ; RV32-NEXT: mv a2, s6 |
| ; RV32-NEXT: li a3, 0 |
| ; RV32-NEXT: call __muldi3 |
| ; RV32-NEXT: lw a1, 88(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: add s5, s5, a1 |
| ; RV32-NEXT: add a0, a0, s2 |
| ; RV32-NEXT: add a0, a0, s4 |
| ; RV32-NEXT: add a0, a0, s3 |
| ; RV32-NEXT: add a0, a0, s7 |
| ; RV32-NEXT: add a0, s5, a0 |
| ; RV32-NEXT: .LBB2_21: # %fp-to-i-cleanup |
| ; RV32-NEXT: zext.b a0, a0 |
| ; RV32-NEXT: lw a1, 116(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a2, 112(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a3, 108(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw a4, 104(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: .LBB2_22: # %fp-to-i-cleanup |
| ; RV32-NEXT: sw a1, 0(s0) |
| ; RV32-NEXT: sw a2, 4(s0) |
| ; RV32-NEXT: sw a3, 8(s0) |
| ; RV32-NEXT: sw a4, 12(s0) |
| ; RV32-NEXT: sw s10, 16(s0) |
| ; RV32-NEXT: sw s11, 20(s0) |
| ; RV32-NEXT: sb a0, 24(s0) |
| ; RV32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s1, 244(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s2, 240(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s3, 236(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s4, 232(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s5, 228(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s6, 224(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s7, 220(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s8, 216(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s9, 212(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s10, 208(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: lw s11, 204(sp) # 4-byte Folded Reload |
| ; RV32-NEXT: addi sp, sp, 256 |
| ; RV32-NEXT: ret |
| %1 = load float, ptr %in, align 4 |
| %2 = fptosi float %1 to i200 |
| store i200 %2, ptr %out, align 8 |
| ret void |
| } |
| |
