llvm/test/CodeGen/PowerPC/ppc-i64-to-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s | \
; RUN:   FileCheck %s --check-prefix=COMMON
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix < %s | \
; RUN:   FileCheck %s --check-prefix=COMMON
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix < %s | \
; RUN:   FileCheck %s --check-prefix=CHECK-AIX32

; Test that assertions related to the range metadata when converting from i64
; to i32 does not occur.

define float @case_i64_uitofp_f32(ptr %p) {
; COMMON-LABEL: case_i64_uitofp_f32:
; COMMON:       # %bb.0: # %entry
; COMMON-NEXT:    lfd f0, 0(r3)
; COMMON-NEXT:    xscvuxdsp f1, f0
; COMMON-NEXT:    blr
;
; CHECK-AIX32-LABEL: case_i64_uitofp_f32:
; CHECK-AIX32:       # %bb.0: # %entry
; CHECK-AIX32-NEXT:    lwz r4, 4(r3)
; CHECK-AIX32-NEXT:    stw r4, -4(r1)
; CHECK-AIX32-NEXT:    lwz r3, 0(r3)
; CHECK-AIX32-NEXT:    stw r3, -8(r1)
; CHECK-AIX32-NEXT:    lfd f0, -8(r1)
; CHECK-AIX32-NEXT:    xscvuxdsp f1, f0
; CHECK-AIX32-NEXT:    blr
entry:
  %x = load i64, ptr %p, align 8, !range !0
  %y = uitofp i64 %x to float
  ret float %y
}

define double @case_i64_sitofp_f64(ptr %p) {
; COMMON-LABEL: case_i64_sitofp_f64:
; COMMON:       # %bb.0: # %entry
; COMMON-NEXT:    lfd f0, 0(r3)
; COMMON-NEXT:    xscvsxddp f1, f0
; COMMON-NEXT:    blr
;
; CHECK-AIX32-LABEL: case_i64_sitofp_f64:
; CHECK-AIX32:       # %bb.0: # %entry
; CHECK-AIX32-NEXT:    lwz r4, 4(r3)
; CHECK-AIX32-NEXT:    stw r4, -4(r1)
; CHECK-AIX32-NEXT:    lwz r3, 0(r3)
; CHECK-AIX32-NEXT:    stw r3, -8(r1)
; CHECK-AIX32-NEXT:    lfd f0, -8(r1)
; CHECK-AIX32-NEXT:    xscvsxddp f1, f0
; CHECK-AIX32-NEXT:    blr
entry:
  %x = load i64, ptr %p, align 8, !range !0
  %y = sitofp i64 %x to double
  ret double %y
}

define double @case_i64_uitofp_f64(ptr %p) {
; COMMON-LABEL: case_i64_uitofp_f64:
; COMMON:       # %bb.0: # %entry
; COMMON-NEXT:    lfd f0, 0(r3)
; COMMON-NEXT:    xscvuxddp f1, f0
; COMMON-NEXT:    blr
;
; CHECK-AIX32-LABEL: case_i64_uitofp_f64:
; CHECK-AIX32:       # %bb.0: # %entry
; CHECK-AIX32-NEXT:    lwz r4, 4(r3)
; CHECK-AIX32-NEXT:    stw r4, -4(r1)
; CHECK-AIX32-NEXT:    lwz r3, 0(r3)
; CHECK-AIX32-NEXT:    stw r3, -8(r1)
; CHECK-AIX32-NEXT:    lfd f0, -8(r1)
; CHECK-AIX32-NEXT:    xscvuxddp f1, f0
; CHECK-AIX32-NEXT:    blr
entry:
  %x = load i64, ptr %p, align 8, !range !0
  %y = uitofp i64 %x to double
  ret double %y
}

define float @case_i64_sitofp_f32(ptr %p) {
; COMMON-LABEL: case_i64_sitofp_f32:
; COMMON:       # %bb.0: # %entry
; COMMON-NEXT:    lfd f0, 0(r3)
; COMMON-NEXT:    xscvsxdsp f1, f0
; COMMON-NEXT:    blr
;
; CHECK-AIX32-LABEL: case_i64_sitofp_f32:
; CHECK-AIX32:       # %bb.0: # %entry
; CHECK-AIX32-NEXT:    lwz r4, 4(r3)
; CHECK-AIX32-NEXT:    stw r4, -4(r1)
; CHECK-AIX32-NEXT:    lwz r3, 0(r3)
; CHECK-AIX32-NEXT:    stw r3, -8(r1)
; CHECK-AIX32-NEXT:    lfd f0, -8(r1)
; CHECK-AIX32-NEXT:    xscvsxdsp f1, f0
; CHECK-AIX32-NEXT:    blr
entry:
  %x = load i64, ptr %p, align 8, !range !0
  %y = sitofp i64 %x to float
  ret float %y
}

!0 = !{i64 1, i64 0}