llvm/test/CodeGen/PowerPC/builtins-ppc-aes-acceleration.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:   -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN:   < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
; RUN:   -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN:   < %s | FileCheck %s

; Generated by AI.

declare <256 x i1> @llvm.ppc.aes.genlastkey.paired(<256 x i1>, i32)
declare <16 x i8> @llvm.ppc.galois.field.mult(<16 x i8>, <16 x i8>, i32)
declare <256 x i1> @llvm.ppc.aes.decrypt.paired(<256 x i1>, <256 x i1>, i32)
declare <256 x i1> @llvm.ppc.aes.encrypt.paired(<256 x i1>, <256 x i1>, i32)

define void @test_aes_encrypt_paired_imm0(ptr %ptr, ptr %vpp1, ptr %vpp2) {
; CHECK-LABEL: test_aes_encrypt_paired_imm0:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lxvp vsp34, 0(r4)
; CHECK-NEXT:    lxvp vsp36, 0(r5)
; CHECK-NEXT:    xxaes128encp vsp34, vsp34, vsp36
; CHECK-NEXT:    stxvp vsp34, 0(r3)
; CHECK-NEXT:    blr
entry:
  %vp1 = load <256 x i1>, ptr %vpp1, align 32
  %vp2 = load <256 x i1>, ptr %vpp2, align 32
  %0 = tail call <256 x i1> @llvm.ppc.aes.encrypt.paired(<256 x i1> %vp1, <256 x i1> %vp2, i32 0)
  store <256 x i1> %0, ptr %ptr, align 32
  ret void
}

define void @test_aes_encrypt_paired_imm1(ptr %ptr, ptr %vpp1, ptr %vpp2) {
; CHECK-LABEL: test_aes_encrypt_paired_imm1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lxvp vsp34, 0(r4)
; CHECK-NEXT:    lxvp vsp36, 0(r5)
; CHECK-NEXT:    xxaes192encp vsp34, vsp34, vsp36
; CHECK-NEXT:    stxvp vsp34, 0(r3)
; CHECK-NEXT:    blr
entry:
  %vp1 = load <256 x i1>, ptr %vpp1, align 32
  %vp2 = load <256 x i1>, ptr %vpp2, align 32
  %0 = tail call <256 x i1> @llvm.ppc.aes.encrypt.paired(<256 x i1> %vp1, <256 x i1> %vp2, i32 1)
  store <256 x i1> %0, ptr %ptr, align 32
  ret void
}

define void @test_aes_encrypt_paired_imm2(ptr %ptr, ptr %vpp1, ptr %vpp2) {
; CHECK-LABEL: test_aes_encrypt_paired_imm2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lxvp vsp34, 0(r4)
; CHECK-NEXT:    lxvp vsp36, 0(r5)
; CHECK-NEXT:    xxaes256encp vsp34, vsp34, vsp36
; CHECK-NEXT:    stxvp vsp34, 0(r3)
; CHECK-NEXT:    blr
entry:
  %vp1 = load <256 x i1>, ptr %vpp1, align 32
  %vp2 = load <256 x i1>, ptr %vpp2, align 32
  %0 = tail call <256 x i1> @llvm.ppc.aes.encrypt.paired(<256 x i1> %vp1, <256 x i1> %vp2, i32 2)
  store <256 x i1> %0, ptr %ptr, align 32
  ret void
}


define void @test_aes_decrypt_paired_imm0(ptr %ptr, ptr %vpp1, ptr %vpp2) {
; CHECK-LABEL: test_aes_decrypt_paired_imm0:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lxvp vsp34, 0(r4)
; CHECK-NEXT:    lxvp vsp36, 0(r5)
; CHECK-NEXT:    xxaes128decp vsp34, vsp34, vsp36
; CHECK-NEXT:    stxvp vsp34, 0(r3)
; CHECK-NEXT:    blr
entry:
  %vp1 = load <256 x i1>, ptr %vpp1, align 32
  %vp2 = load <256 x i1>, ptr %vpp2, align 32
  %0 = tail call <256 x i1> @llvm.ppc.aes.decrypt.paired(<256 x i1> %vp1, <256 x i1> %vp2, i32 0)
  store <256 x i1> %0, ptr %ptr, align 32
  ret void
}

define void @test_aes_decrypt_paired_imm1(ptr %ptr, ptr %vpp1, ptr %vpp2) {
; CHECK-LABEL: test_aes_decrypt_paired_imm1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lxvp vsp34, 0(r4)
; CHECK-NEXT:    lxvp vsp36, 0(r5)
; CHECK-NEXT:    xxaes192decp vsp34, vsp34, vsp36
; CHECK-NEXT:    stxvp vsp34, 0(r3)
; CHECK-NEXT:    blr
entry:
  %vp1 = load <256 x i1>, ptr %vpp1, align 32
  %vp2 = load <256 x i1>, ptr %vpp2, align 32
  %0 = tail call <256 x i1> @llvm.ppc.aes.decrypt.paired(<256 x i1> %vp1, <256 x i1> %vp2, i32 1)
  store <256 x i1> %0, ptr %ptr, align 32
  ret void
}

define void @test_aes_decrypt_paired_imm2(ptr %ptr, ptr %vpp1, ptr %vpp2) {
; CHECK-LABEL: test_aes_decrypt_paired_imm2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lxvp vsp34, 0(r4)
; CHECK-NEXT:    lxvp vsp36, 0(r5)
; CHECK-NEXT:    xxaes256decp vsp34, vsp34, vsp36
; CHECK-NEXT:    stxvp vsp34, 0(r3)
; CHECK-NEXT:    blr
entry:
  %vp1 = load <256 x i1>, ptr %vpp1, align 32
  %vp2 = load <256 x i1>, ptr %vpp2, align 32
  %0 = tail call <256 x i1> @llvm.ppc.aes.decrypt.paired(<256 x i1> %vp1, <256 x i1> %vp2, i32 2)
  store <256 x i1> %0, ptr %ptr, align 32
  ret void
}


define void @test_aes_genlastkey_paired_imm0(ptr %ptr, ptr %vpp1) {
; CHECK-LABEL: test_aes_genlastkey_paired_imm0:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lxvp vsp34, 0(r4)
; CHECK-NEXT:    xxaes128genlkp vsp34, vsp34
; CHECK-NEXT:    stxvp vsp34, 0(r3)
; CHECK-NEXT:    blr
entry:
  %vp1 = load <256 x i1>, ptr %vpp1, align 32
  %0 = tail call <256 x i1> @llvm.ppc.aes.genlastkey.paired(<256 x i1> %vp1, i32 0)
  store <256 x i1> %0, ptr %ptr, align 32
  ret void
}

define void @test_aes_genlastkey_paired_imm1(ptr %ptr, ptr %vpp1) {
; CHECK-LABEL: test_aes_genlastkey_paired_imm1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lxvp vsp34, 0(r4)
; CHECK-NEXT:    xxaes192genlkp vsp34, vsp34
; CHECK-NEXT:    stxvp vsp34, 0(r3)
; CHECK-NEXT:    blr
entry:
  %vp1 = load <256 x i1>, ptr %vpp1, align 32
  %0 = tail call <256 x i1> @llvm.ppc.aes.genlastkey.paired(<256 x i1> %vp1, i32 1)
  store <256 x i1> %0, ptr %ptr, align 32
  ret void
}

define void @test_aes_genlastkey_paired_imm2(ptr %ptr, ptr %vpp1) {
; CHECK-LABEL: test_aes_genlastkey_paired_imm2:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lxvp vsp34, 0(r4)
; CHECK-NEXT:    xxaes256genlkp vsp34, vsp34
; CHECK-NEXT:    stxvp vsp34, 0(r3)
; CHECK-NEXT:    blr
entry:
  %vp1 = load <256 x i1>, ptr %vpp1, align 32
  %0 = tail call <256 x i1> @llvm.ppc.aes.genlastkey.paired(<256 x i1> %vp1, i32 2)
  store <256 x i1> %0, ptr %ptr, align 32
  ret void
}

define <16 x i8> @test_galois_field_mult_imm0(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_galois_field_mult_imm0:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxgfmul128gcm v2, v2, v3
; CHECK-NEXT:    blr
entry:
  %0 = tail call <16 x i8> @llvm.ppc.galois.field.mult(<16 x i8> %a, <16 x i8> %b, i32 0)
  ret <16 x i8> %0
}

define <16 x i8> @test_galois_field_mult_imm1(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_galois_field_mult_imm1:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xxgfmul128xts v2, v2, v3
; CHECK-NEXT:    blr
entry:
  %0 = tail call <16 x i8> @llvm.ppc.galois.field.mult(<16 x i8> %a, <16 x i8> %b, i32 1)
  ret <16 x i8> %0
}