llvm/test/CodeGen/NVPTX/tcgen05-commit-sm107.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -march=nvptx64 -mcpu=sm_107f  | FileCheck --check-prefixes=CHECK_PTX64 %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_107f -target-abi=shortptr | FileCheck --check-prefixes=CHECK_PTX64_SHARED32 %s

; RUN: %if ptxas-sm_107f && ptxas-isa-9.4 %{ llc < %s -march=nvptx64 -mcpu=sm_107f  | %ptxas-verify -arch=sm_107f %}
; RUN: %if ptxas-sm_107f && ptxas-isa-9.4 %{ llc < %s -march=nvptx64 -mcpu=sm_107f -target-abi=shortptr | %ptxas-verify -arch=sm_107f %}

declare void @llvm.nvvm.tcgen05.commit.smem.a.read.cg1.p0(ptr %bar_addr)
declare void @llvm.nvvm.tcgen05.commit.smem.a.read.cg2.p0(ptr %bar_addr)
declare void @llvm.nvvm.tcgen05.commit.smem.a.read.cg1.p3(ptr addrspace(3) %bar_addr)
declare void @llvm.nvvm.tcgen05.commit.smem.a.read.cg2.p3(ptr addrspace(3) %bar_addr)

define void @test_tcgen05_commit_smem_a_read_cg1(ptr %bar_addr) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_cg1(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg1_param_0];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_cg1(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg1_param_0];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.cg1.p0(ptr %bar_addr)

  ret void
}

define void @test_tcgen05_commit_smem_a_read_cg2(ptr %bar_addr) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_cg2(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg2_param_0];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_cg2(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg2_param_0];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.cg2.p0(ptr %bar_addr)

  ret void
}

define void @test_tcgen05_commit_smem_a_read_shared_cg1(ptr addrspace(3) %bar_addr) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_shared_cg1(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_shared_cg1_param_0];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_shared_cg1(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_shared_cg1_param_0];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%r1];
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.cg1.p3(ptr addrspace(3) %bar_addr)

  ret void
}

define void @test_tcgen05_commit_smem_a_read_shared_cg2(ptr addrspace(3) %bar_addr) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_shared_cg2(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_shared_cg2_param_0];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_shared_cg2(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_shared_cg2_param_0];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%r1];
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.cg2.p3(ptr addrspace(3) %bar_addr)

  ret void
}

declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p0.i16(ptr %bar_addr, i16 %cta_mask)
declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p0.i16(ptr %bar_addr, i16 %cta_mask)
declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p3.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)
declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p3.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)

define void @test_tcgen05_commit_smem_a_read_mc_cg1(ptr %bar_addr, i16 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_cg1(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b16 %rs<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_cg1(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b16 %rs<2>;
; CHECK_PTX64_SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p0.i16(ptr %bar_addr, i16 %cta_mask)

  ret void
}

define void @test_tcgen05_commit_smem_a_read_mc_cg2(ptr %bar_addr, i16 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_cg2(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b16 %rs<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_cg2(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b16 %rs<2>;
; CHECK_PTX64_SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p0.i16(ptr %bar_addr, i16 %cta_mask)

  ret void
}

define void @test_tcgen05_commit_smem_a_read_mc_shared_cg1(ptr addrspace(3) %bar_addr, i16 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg1(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b16 %rs<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg1(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b16 %rs<2>;
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%r1], %rs1;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p3.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)

  ret void
}

define void @test_tcgen05_commit_smem_a_read_mc_shared_cg2(ptr addrspace(3) %bar_addr, i16 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg2(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b16 %rs<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg2(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b16 %rs<2>;
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%r1], %rs1;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p3.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)

  ret void
}

declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p0.i32(ptr %bar_addr, i32 %cta_mask)
declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p0.i32(ptr %bar_addr, i32 %cta_mask)
declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
declare void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)

define void @test_tcgen05_commit_smem_a_read_mc_cg1_i32(ptr %bar_addr, i32 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_cg1_i32(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_cg1_i32(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p0.i32(ptr %bar_addr, i32 %cta_mask)

  ret void
}

define void @test_tcgen05_commit_smem_a_read_mc_cg2_i32(ptr %bar_addr, i32 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_cg2_i32(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_cg2_i32(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p0.i32(ptr %bar_addr, i32 %cta_mask)

  ret void
}

define void @test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32(ptr addrspace(3) %bar_addr, i32 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r2, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%r1], %r2;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)

  ret void
}

define void @test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32(ptr addrspace(3) %bar_addr, i32 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r2, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%r1], %r2;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)

  ret void
}

declare void @llvm.nvvm.tcgen05.commit.mc.cg1.p0.i32(ptr %bar_addr, i32 %cta_mask)
declare void @llvm.nvvm.tcgen05.commit.mc.cg2.p0.i32(ptr %bar_addr, i32 %cta_mask)
declare void @llvm.nvvm.tcgen05.commit.mc.cg1.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
declare void @llvm.nvvm.tcgen05.commit.mc.cg2.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)

define void @test_tcgen05_commit_mc_cg1_i32(ptr %bar_addr, i32 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_mc_cg1_i32(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg1_i32_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_mc_cg1_i32_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_mc_cg1_i32(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg1_i32_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_mc_cg1_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.mc.cg1.p0.i32(ptr %bar_addr, i32 %cta_mask)

  ret void
}

define void @test_tcgen05_commit_mc_cg2_i32(ptr %bar_addr, i32 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_mc_cg2_i32(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg2_i32_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_mc_cg2_i32_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_mc_cg2_i32(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg2_i32_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_mc_cg2_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.mc.cg2.p0.i32(ptr %bar_addr, i32 %cta_mask)

  ret void
}

define void @test_tcgen05_commit_mc_shared_cg1_i32(ptr addrspace(3) %bar_addr, i32 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_mc_shared_cg1_i32(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_shared_cg1_i32_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_mc_shared_cg1_i32_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_mc_shared_cg1_i32(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_mc_shared_cg1_i32_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r2, [test_tcgen05_commit_mc_shared_cg1_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%r1], %r2;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.mc.cg1.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)

  ret void
}

define void @test_tcgen05_commit_mc_shared_cg2_i32(ptr addrspace(3) %bar_addr, i32 %cta_mask) {
; CHECK_PTX64-LABEL: test_tcgen05_commit_mc_shared_cg2_i32(
; CHECK_PTX64:       {
; CHECK_PTX64-NEXT:    .reg .b32 %r<2>;
; CHECK_PTX64-NEXT:    .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT:  // %bb.0:
; CHECK_PTX64-NEXT:    ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_shared_cg2_i32_param_0];
; CHECK_PTX64-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_mc_shared_cg2_i32_param_1];
; CHECK_PTX64-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT:    ret;
;
; CHECK_PTX64_SHARED32-LABEL: test_tcgen05_commit_mc_shared_cg2_i32(
; CHECK_PTX64_SHARED32:       {
; CHECK_PTX64_SHARED32-NEXT:    .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT:  // %bb.0:
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r1, [test_tcgen05_commit_mc_shared_cg2_i32_param_0];
; CHECK_PTX64_SHARED32-NEXT:    ld.param::func.b32 %r2, [test_tcgen05_commit_mc_shared_cg2_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT:    tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%r1], %r2;
; CHECK_PTX64_SHARED32-NEXT:    ret;
  call void @llvm.nvvm.tcgen05.commit.mc.cg2.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)

  ret void
}