llvm/test/CodeGen/AMDGPU/merge-image-load-dim.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -mtriple=amdgpu11.00 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -mtriple=amdgpu12.00 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX12 %s

; Mismatched dim must block merging: would reinterpret the array slice as y.

define amdgpu_ps <4 x float> @load_2d_1darray_dim_mismatch(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; GFX10-LABEL: load_2d_1darray_dim_mismatch:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    v_mov_b32_e32 v4, v1
; GFX10-NEXT:    s_clause 0x1
; GFX10-NEXT:    image_load v5, v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm
; GFX10-NEXT:    image_load v[1:3], v[0:1], s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D_ARRAY unorm
; GFX10-NEXT:    ; kill: killed $vgpr4
; GFX10-NEXT:    s_waitcnt vmcnt(1)
; GFX10-NEXT:    v_mov_b32_e32 v0, v5
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    ; return to shader part epilog
;
; GFX11-LABEL: load_2d_1darray_dim_mismatch:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    s_clause 0x1
; GFX11-NEXT:    image_load v4, v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm
; GFX11-NEXT:    image_load v[1:3], v[0:1], s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D_ARRAY unorm
; GFX11-NEXT:    s_waitcnt vmcnt(1)
; GFX11-NEXT:    v_mov_b32_e32 v0, v4
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    ; return to shader part epilog
;
; GFX12-LABEL: load_2d_1darray_dim_mismatch:
; GFX12:       ; %bb.0: ; %main_body
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    image_load v4, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX12-NEXT:    image_load v[1:3], [v0, v1], s[0:7] dmask:0xe dim:SQ_RSRC_IMG_1D_ARRAY
; GFX12-NEXT:    s_wait_loadcnt 0x1
; GFX12-NEXT:    v_mov_b32_e32 v0, v4
; GFX12-NEXT:    s_wait_loadcnt 0x0
; GFX12-NEXT:    ; return to shader part epilog
main_body:
  %v1 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %v2 = call <3 x float> @llvm.amdgcn.image.load.1darray.v3f32.i32(i32 14, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %e0 = extractelement <3 x float> %v2, i32 0
  %e1 = extractelement <3 x float> %v2, i32 1
  %e2 = extractelement <3 x float> %v2, i32 2
  %r0 = insertelement <4 x float> poison, float %v1, i32 0
  %r1 = insertelement <4 x float> %r0, float %e0, i32 1
  %r2 = insertelement <4 x float> %r1, float %e1, i32 2
  %r3 = insertelement <4 x float> %r2, float %e2, i32 3
  ret <4 x float> %r3
}

; Matching dim: merging still expected.

define amdgpu_ps <4 x float> @load_2d_2d_merged(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
; GFX10-LABEL: load_2d_2d_merged:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    ; return to shader part epilog
;
; GFX11-LABEL: load_2d_2d_merged:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    ; return to shader part epilog
;
; GFX12-LABEL: load_2d_2d_merged:
; GFX12:       ; %bb.0: ; %main_body
; GFX12-NEXT:    image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX12-NEXT:    s_wait_loadcnt 0x0
; GFX12-NEXT:    ; return to shader part epilog
main_body:
  %v1 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %v2 = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 14, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  %e0 = extractelement <3 x float> %v2, i32 0
  %e1 = extractelement <3 x float> %v2, i32 1
  %e2 = extractelement <3 x float> %v2, i32 2
  %r0 = insertelement <4 x float> poison, float %v1, i32 0
  %r1 = insertelement <4 x float> %r0, float %e0, i32 1
  %r2 = insertelement <4 x float> %r1, float %e1, i32 2
  %r3 = insertelement <4 x float> %r2, float %e2, i32 3
  ret <4 x float> %r3
}

declare float @llvm.amdgcn.image.load.2d.f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #0
declare <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #0
declare <3 x float> @llvm.amdgcn.image.load.1darray.v3f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #0

attributes #0 = { nounwind readonly }