llvm/test/CodeGen/AMDGPU/llvm.amdgcn.add.min.max.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250-GISEL %s

declare i32 @llvm.amdgcn.add.min.i32(i32, i32, i32, i1)
declare i32 @llvm.amdgcn.add.max.i32(i32, i32, i32, i1)
declare i32 @llvm.amdgcn.add.min.u32(i32, i32, i32, i1)
declare i32 @llvm.amdgcn.add.max.u32(i32, i32, i32, i1)
declare <2 x i16> @llvm.amdgcn.pk.add.min.i16(<2 x i16>, <2 x i16>, <2 x i16>, i1)
declare <2 x i16> @llvm.amdgcn.pk.add.max.i16(<2 x i16>, <2 x i16>, <2 x i16>, i1)
declare <2 x i16> @llvm.amdgcn.pk.add.min.u16(<2 x i16>, <2 x i16>, <2 x i16>, i1)
declare <2 x i16> @llvm.amdgcn.pk.add.max.u16(<2 x i16>, <2 x i16>, <2 x i16>, i1)

define i32 @test_add_min_i32_vvv(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: test_add_min_i32_vvv:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_add_min_i32 v0, v0, v1, v2
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call i32 @llvm.amdgcn.add.min.i32(i32 %a, i32 %b, i32 %c, i1 0)
  ret i32 %ret
}

define i32 @test_add_min_i32_ssi_clamp(i32 inreg %a, i32 inreg %b) {
; GCN-LABEL: test_add_min_i32_ssi_clamp:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_add_min_i32 v0, s0, s1, 1 clamp
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call i32 @llvm.amdgcn.add.min.i32(i32 %a, i32 %b, i32 1, i1 1)
  ret i32 %ret
}

define i32 @test_add_min_u32_vvv(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: test_add_min_u32_vvv:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_add_min_u32 v0, v0, v1, v2
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call i32 @llvm.amdgcn.add.min.u32(i32 %a, i32 %b, i32 %c, i1 0)
  ret i32 %ret
}

define i32 @test_add_min_u32_ssi_clamp(i32 inreg %a, i32 inreg %b) {
; GCN-LABEL: test_add_min_u32_ssi_clamp:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_add_min_u32 v0, s0, s1, 1 clamp
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call i32 @llvm.amdgcn.add.min.u32(i32 %a, i32 %b, i32 1, i1 1)
  ret i32 %ret
}

define i32 @test_add_max_i32_vvv(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: test_add_max_i32_vvv:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_add_max_i32 v0, v0, v1, v2
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call i32 @llvm.amdgcn.add.max.i32(i32 %a, i32 %b, i32 %c, i1 0)
  ret i32 %ret
}

define i32 @test_add_max_i32_ssi_clamp(i32 inreg %a, i32 inreg %b) {
; GCN-LABEL: test_add_max_i32_ssi_clamp:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_add_max_i32 v0, s0, s1, 1 clamp
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call i32 @llvm.amdgcn.add.max.i32(i32 %a, i32 %b, i32 1, i1 1)
  ret i32 %ret
}

define i32 @test_add_max_u32_vvv(i32 %a, i32 %b, i32 %c) {
; GCN-LABEL: test_add_max_u32_vvv:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_add_max_u32 v0, v0, v1, v2
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call i32 @llvm.amdgcn.add.max.u32(i32 %a, i32 %b, i32 %c, i1 0)
  ret i32 %ret
}

define i32 @test_add_max_u32_ssi_clamp(i32 inreg %a, i32 inreg %b) {
; GCN-LABEL: test_add_max_u32_ssi_clamp:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_add_max_u32 v0, s0, s1, 1 clamp
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call i32 @llvm.amdgcn.add.max.u32(i32 %a, i32 %b, i32 1, i1 1)
  ret i32 %ret
}

define <2 x i16> @test_add_min_i16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GCN-LABEL: test_add_min_i16_vvv:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_pk_add_min_i16 v0, v0, v1, v2
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.min.i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, i1 0)
  ret <2 x i16> %ret
}

define <2 x i16> @test_add_min_i16_ssi_clamp(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GCN-LABEL: test_add_min_i16_ssi_clamp:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_pk_add_min_i16 v0, s0, s1, 1 op_sel_hi:[1,1,0] clamp
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.min.i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> <i16 1, i16 1>, i1 1)
  ret <2 x i16> %ret
}

define <2 x i16> @test_add_min_u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GCN-LABEL: test_add_min_u16_vvv:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_pk_add_min_u16 v0, v0, v1, v2
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.min.u16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, i1 0)
  ret <2 x i16> %ret
}

define <2 x i16> @test_add_min_u16_ssi_clamp(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GCN-LABEL: test_add_min_u16_ssi_clamp:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_pk_add_min_u16 v0, s0, s1, 1 op_sel_hi:[1,1,0] clamp
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.min.u16(<2 x i16> %a, <2 x i16> %b, <2 x i16> <i16 1, i16 1>, i1 1)
  ret <2 x i16> %ret
}

define <2 x i16> @test_add_max_i16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GCN-LABEL: test_add_max_i16_vvv:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_pk_add_max_i16 v0, v0, v1, v2
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.max.i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, i1 0)
  ret <2 x i16> %ret
}

define <2 x i16> @test_add_max_i16_ssi_clamp(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GCN-LABEL: test_add_max_i16_ssi_clamp:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_pk_add_max_i16 v0, s0, s1, 1 op_sel_hi:[1,1,0] clamp
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.max.i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> <i16 1, i16 1>, i1 1)
  ret <2 x i16> %ret
}

define <2 x i16> @test_add_max_u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
; GCN-LABEL: test_add_max_u16_vvv:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_pk_add_max_u16 v0, v0, v1, v2
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.max.u16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, i1 0)
  ret <2 x i16> %ret
}

define <2 x i16> @test_add_max_u16_ssi_clamp(<2 x i16> inreg %a, <2 x i16> inreg %b) {
; GCN-LABEL: test_add_max_u16_ssi_clamp:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_wait_loadcnt_dscnt 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_pk_add_max_u16 v0, s0, s1, 1 op_sel_hi:[1,1,0] clamp
; GCN-NEXT:    s_set_pc_i64 s[30:31]
  %ret = tail call <2 x i16> @llvm.amdgcn.pk.add.max.u16(<2 x i16> %a, <2 x i16> %b, <2 x i16> <i16 1, i16 1>, i1 1)
  ret <2 x i16> %ret
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1250-GISEL: {{.*}}
; GFX1250-SDAG: {{.*}}