llvm/test/CodeGen/AMDGPU/insert-delay-alu-ldsdma.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# Verify LDSDMA delay-alu handling: LDSDMA consumes VALU delay state on its
# SGPR operands but must not publish VALU delay state from its defs.
# RUN: llc -mtriple=amdgpu12.50 -run-pass=amdgpu-insert-delay-alu %s -o - | FileCheck %s

---
name: ldsdma_consumer_needs_delay
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
    ; CHECK-LABEL: name: ldsdma_consumer_needs_delay
    ; CHECK: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: $exec = IMPLICIT_DEF
    ; CHECK-NEXT: $sgpr0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
    ; CHECK-NEXT: S_DELAY_ALU .id0_VALU_DEP_1
    ; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
    ; CHECK-NEXT: S_ENDPGM 0
    $exec = IMPLICIT_DEF
    $sgpr0 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
    TENSOR_LOAD_TO_LDS_d2_gfx1250 $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
    S_ENDPGM 0
...

---
name: ldsdma_not_valu_producer
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
    ; CHECK-LABEL: name: ldsdma_not_valu_producer
    ; CHECK: liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: $exec = IMPLICIT_DEF
    ; CHECK-NEXT: $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec
    ; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
    ; CHECK-NEXT: S_DELAY_ALU .id0_VALU_DEP_1
    ; CHECK-NEXT: $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    $exec = IMPLICIT_DEF
    $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec
    TENSOR_LOAD_TO_LDS_d2_gfx1250 $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
    $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec
    S_ENDPGM 0
...