llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu9.0a -O1 -global-isel < %s | FileCheck %s

; Test that V_INDIRECT_REG_READ_GPR_IDX expansion handles immediate index operands.
; The wave.reduce.umin with constant arguments folds to 0, which becomes an
; immediate index for the insertelement, triggering V_INDIRECT_REG_READ_GPR_IDX
; with an immediate operand.

define amdgpu_kernel void @indirect_reg_read_imm_idx() {
; CHECK-LABEL: indirect_reg_read_imm_idx:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    v_pk_mov_b32 v[0:1], 0, 0
; CHECK-NEXT:    v_mov_b32_e32 v4, 16
; CHECK-NEXT:    v_mov_b32_e32 v5, 0
; CHECK-NEXT:    v_mov_b32_e32 v8, 32
; CHECK-NEXT:    v_mov_b32_e32 v9, 0
; CHECK-NEXT:    v_mov_b32_e32 v12, 48
; CHECK-NEXT:    v_mov_b32_e32 v13, 0
; CHECK-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]
; CHECK-NEXT:    s_nop 0
; CHECK-NEXT:    flat_load_dwordx4 v[4:7], v[4:5]
; CHECK-NEXT:    s_nop 0
; CHECK-NEXT:    flat_load_dwordx4 v[8:11], v[8:9]
; CHECK-NEXT:    s_nop 0
; CHECK-NEXT:    flat_load_dwordx4 v[12:15], v[12:13]
; CHECK-NEXT:    s_mov_b32 s0, 0xffff
; CHECK-NEXT:    v_pk_mov_b32 v[16:17], 0, 0
; CHECK-NEXT:    v_mov_b32_e32 v18, 16
; CHECK-NEXT:    v_mov_b32_e32 v19, 0
; CHECK-NEXT:    v_mov_b32_e32 v20, 32
; CHECK-NEXT:    v_mov_b32_e32 v21, 0
; CHECK-NEXT:    v_mov_b32_e32 v22, 48
; CHECK-NEXT:    v_mov_b32_e32 v23, 0
; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_set_gpr_idx_on 0, gpr_idx(SRC0)
; CHECK-NEXT:    v_mov_b32_e32 v24, v0
; CHECK-NEXT:    s_set_gpr_idx_off
; CHECK-NEXT:    v_bfi_b32 v24, s0, 0, v24
; CHECK-NEXT:    s_set_gpr_idx_on 0, gpr_idx(DST)
; CHECK-NEXT:    v_mov_b32_e32 v0, v24
; CHECK-NEXT:    s_set_gpr_idx_off
; CHECK-NEXT:    flat_store_dwordx4 v[16:17], v[0:3]
; CHECK-NEXT:    flat_store_dwordx4 v[18:19], v[4:7]
; CHECK-NEXT:    flat_store_dwordx4 v[20:21], v[8:11]
; CHECK-NEXT:    flat_store_dwordx4 v[22:23], v[12:15]
; CHECK-NEXT:    s_endpgm
entry:
  %vec = load <32 x i16>, ptr null, align 64
  %idx = call i32 @llvm.amdgcn.wave.reduce.umin.i32(i32 0, i32 0)
  %ins = insertelement <32 x i16> %vec, i16 0, i32 %idx
  store <32 x i16> %ins, ptr null, align 64
  ret void
}

declare i32 @llvm.amdgcn.wave.reduce.umin.i32(i32, i32 immarg)