llvm/test/CodeGen/AMDGPU/function-esm2-prologue-epilogue.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1200 -amdgpu-expert-scheduling-mode=0 | FileCheck %s --check-prefix=GFX12
; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1200 -amdgpu-expert-scheduling-mode=1 | FileCheck %s --check-prefix=GFX12-ESM

; Check for s_setreg_imm32_b32 on function entry and return and around calls.
; Check for s_wait_alu on non-kernel function entry and return.

define float @missing_truncate_promote_bswap(i32 %arg) {
; GFX12-LABEL: missing_truncate_promote_bswap:
; GFX12:       ; %bb.0: ; %bb
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_perm_b32 v0, 0, v0, 0xc0c0001
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ESM-LABEL: missing_truncate_promote_bswap:
; GFX12-ESM:       ; %bb.0: ; %bb
; GFX12-ESM-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE, 0, 2), 2
; GFX12-ESM-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ESM-NEXT:    s_wait_expcnt 0x0
; GFX12-ESM-NEXT:    s_wait_samplecnt 0x0
; GFX12-ESM-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ESM-NEXT:    s_wait_kmcnt 0x0
; GFX12-ESM-NEXT:    v_perm_b32 v0, 0, v0, 0xc0c0001
; GFX12-ESM-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-ESM-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX12-ESM-NEXT:    s_wait_alu depctr_va_vdst(0)
; GFX12-ESM-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE, 0, 2), 0
; GFX12-ESM-NEXT:    s_setpc_b64 s[30:31]
bb:
  %tmp = trunc i32 %arg to i16
  %tmp1 = call i16 @llvm.bswap.i16(i16 %tmp)
  %tmp2 = bitcast i16 %tmp1 to half
  %tmp3 = fpext half %tmp2 to float
  ret float %tmp3
}

define amdgpu_kernel void @main(i32 %arg) {
; GFX12-LABEL: main:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b32 s14, s[4:5], 0x24
; GFX12-NEXT:    s_mov_b64 s[10:11], s[6:7]
; GFX12-NEXT:    s_getpc_b64 s[6:7]
; GFX12-NEXT:    s_sext_i32_i16 s7, s7
; GFX12-NEXT:    s_add_co_u32 s6, s6, missing_truncate_promote_bswap@gotpcrel32@lo+8
; GFX12-NEXT:    s_add_co_ci_u32 s7, s7, missing_truncate_promote_bswap@gotpcrel32@hi+16
; GFX12-NEXT:    v_mov_b32_e32 v31, v0
; GFX12-NEXT:    s_load_b64 s[12:13], s[6:7], 0x0
; GFX12-NEXT:    s_add_nc_u64 s[8:9], s[4:5], 40
; GFX12-NEXT:    s_mov_b64 s[4:5], s[0:1]
; GFX12-NEXT:    s_mov_b64 s[6:7], s[2:3]
; GFX12-NEXT:    s_mov_b32 s32, 0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_mov_b32_e32 v0, s14
; GFX12-NEXT:    s_swappc_b64 s[30:31], s[12:13]
; GFX12-NEXT:    s_endpgm
;
; GFX12-ESM-LABEL: main:
; GFX12-ESM:       ; %bb.0:
; GFX12-ESM-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE, 0, 2), 2
; GFX12-ESM-NEXT:    s_load_b32 s14, s[4:5], 0x24
; GFX12-ESM-NEXT:    s_mov_b64 s[10:11], s[6:7]
; GFX12-ESM-NEXT:    s_getpc_b64 s[6:7]
; GFX12-ESM-NEXT:    s_sext_i32_i16 s7, s7
; GFX12-ESM-NEXT:    s_add_co_u32 s6, s6, missing_truncate_promote_bswap@gotpcrel32@lo+8
; GFX12-ESM-NEXT:    s_add_co_ci_u32 s7, s7, missing_truncate_promote_bswap@gotpcrel32@hi+16
; GFX12-ESM-NEXT:    v_mov_b32_e32 v31, v0
; GFX12-ESM-NEXT:    s_load_b64 s[12:13], s[6:7], 0x0
; GFX12-ESM-NEXT:    s_add_nc_u64 s[8:9], s[4:5], 40
; GFX12-ESM-NEXT:    s_mov_b64 s[4:5], s[0:1]
; GFX12-ESM-NEXT:    s_mov_b64 s[6:7], s[2:3]
; GFX12-ESM-NEXT:    s_mov_b32 s32, 0
; GFX12-ESM-NEXT:    s_wait_kmcnt 0x0
; GFX12-ESM-NEXT:    v_mov_b32_e32 v0, s14
; GFX12-ESM-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE, 0, 2), 0
; GFX12-ESM-NEXT:    s_swappc_b64 s[30:31], s[12:13]
; GFX12-ESM-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE, 0, 2), 2
; GFX12-ESM-NEXT:    s_endpgm
  %tmp = call float @missing_truncate_promote_bswap(i32 %arg)
  ret void
}