llvm/test/CodeGen/AMDGPU/fold-sgpr-splat-pk64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgpu12.51 -run-pass=si-fold-operands -o - %s | FileCheck --check-prefix=GFX1251 %s

---
name:            pk_add_f64_vgpr_splat_sgpr
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1

    ; GFX1251-LABEL: name: pk_add_f64_vgpr_splat_sgpr
    ; GFX1251: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1
    ; GFX1251-NEXT: {{  $}}
    ; GFX1251-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; GFX1251-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX1251-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, undef %5:sreg_64, %subreg.sub2_sub3
    ; GFX1251-NEXT: [[V_PK_ADD_F64_:%[0-9]+]]:vreg_128_align2 = nofpexcept V_PK_ADD_F64 8, killed [[COPY]], 0, killed [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
    ; GFX1251-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_F64_]]
    %0:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:sreg_64 = COPY $sgpr0_sgpr1
    %2:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0_sub1, killed %1, %subreg.sub2_sub3
    %3:vreg_128_align2 = nofpexcept V_PK_ADD_F64 8, killed %0, 0, killed %2, 0, 0, 0, implicit $mode, implicit $exec
    S_ENDPGM 0, implicit %3
...

---
name:            pk_add_f64_vgpr_non_splat_sgpr
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1, $sgpr2_sgpr3

    ; GFX1251-LABEL: name: pk_add_f64_vgpr_non_splat_sgpr
    ; GFX1251: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1, $sgpr2_sgpr3
    ; GFX1251-NEXT: {{  $}}
    ; GFX1251-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; GFX1251-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX1251-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; GFX1251-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY1]], %subreg.sub0_sub1, killed [[COPY2]], %subreg.sub2_sub3
    ; GFX1251-NEXT: [[V_PK_ADD_F64_:%[0-9]+]]:vreg_128_align2 = nofpexcept V_PK_ADD_F64 8, killed [[COPY]], 0, killed [[REG_SEQUENCE]], 0, 0, 0, implicit $mode, implicit $exec
    ; GFX1251-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_F64_]]
    %0:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:sreg_64 = COPY $sgpr0_sgpr1
    %2:sreg_64 = COPY $sgpr2_sgpr3
    %3:sgpr_128 = REG_SEQUENCE killed %1, %subreg.sub0_sub1, killed %2, %subreg.sub2_sub3
    %4:vreg_128_align2 = nofpexcept V_PK_ADD_F64 8, killed %0, 0, killed %3, 0, 0, 0, implicit $mode, implicit $exec
    S_ENDPGM 0, implicit %4
...

---
name:            pk_add_u64_vgpr_splat_sgpr
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1

    ; GFX1251-LABEL: name: pk_add_u64_vgpr_splat_sgpr
    ; GFX1251: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1
    ; GFX1251-NEXT: {{  $}}
    ; GFX1251-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; GFX1251-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX1251-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0_sub1, undef %5:sreg_64, %subreg.sub2_sub3
    ; GFX1251-NEXT: [[V_PK_ADD_NC_U64_:%[0-9]+]]:vreg_128_align2 = V_PK_ADD_NC_U64 8, killed [[COPY]], 0, killed [[REG_SEQUENCE]], 0, 0, 0, implicit $exec
    ; GFX1251-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_NC_U64_]]
    %0:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:sreg_64 = COPY $sgpr0_sgpr1
    %2:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0_sub1, killed %1, %subreg.sub2_sub3
    %3:vreg_128_align2 = V_PK_ADD_NC_U64 8, killed %0, 0, killed %2, 0, 0, 0, implicit $exec
    S_ENDPGM 0, implicit %3
...

---
name:            pk_add_u64_vgpr_non_splat_sgpr
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1, $sgpr2_sgpr3

    ; GFX1251-LABEL: name: pk_add_u64_vgpr_non_splat_sgpr
    ; GFX1251: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0_sgpr1, $sgpr2_sgpr3
    ; GFX1251-NEXT: {{  $}}
    ; GFX1251-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; GFX1251-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX1251-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; GFX1251-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE killed [[COPY1]], %subreg.sub0_sub1, killed [[COPY2]], %subreg.sub2_sub3
    ; GFX1251-NEXT: [[V_PK_ADD_NC_U64_:%[0-9]+]]:vreg_128_align2 = V_PK_ADD_NC_U64 8, killed [[COPY]], 0, killed [[REG_SEQUENCE]], 0, 0, 0, implicit $exec
    ; GFX1251-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_NC_U64_]]
    %0:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:sreg_64 = COPY $sgpr0_sgpr1
    %2:sreg_64 = COPY $sgpr2_sgpr3
    %3:sgpr_128 = REG_SEQUENCE killed %1, %subreg.sub0_sub1, killed %2, %subreg.sub2_sub3
    %4:vreg_128_align2 = V_PK_ADD_NC_U64 8, killed %0, 0, killed %3, 0, 0, 0, implicit $exec
    S_ENDPGM 0, implicit %4
...