llvm/test/CodeGen/AMDGPU/expand-mov-b64-globaladdr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgpu10.10--amdpal < %s | FileCheck --check-prefix=GFX10 %s
; RUN: llc -mtriple=amdgpu11.00--amdpal < %s | FileCheck --check-prefix=GFX11 %s

; Verify that V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO are expanded into a
; pair of 32-bit moves of the absolute hi/lo halves of a global address when
; the subtarget does not support 64-bit literals.

@gv = external addrspace(4) constant [6 x i32]

; Divergent select of @gv lowers to V_MOV_B64_PSEUDO with a GlobalAddress
; operand which expandPostRAPseudo splits into v_mov_b32 abs32@lo/@hi.
define amdgpu_ps ptr addrspace(4) @v_mov_b64_pseudo_globaladdr(i1 %cond) {
; GFX10-LABEL: v_mov_b64_pseudo_globaladdr:
; GFX10:       ; %bb.0: ; %entry
; GFX10-NEXT:    v_and_b32_e32 v2, 1, v0
; GFX10-NEXT:    v_mov_b32_e32 v0, 0
; GFX10-NEXT:    v_mov_b32_e32 v1, 0
; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT:    s_and_saveexec_b32 s0, vcc_lo
; GFX10-NEXT:  ; %bb.1: ; %other
; GFX10-NEXT:    v_mov_b32_e32 v0, gv@abs32@lo
; GFX10-NEXT:    v_mov_b32_e32 v1, gv@abs32@hi
; GFX10-NEXT:  ; %bb.2: ; %join
; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
; GFX10-NEXT:    ; return to shader part epilog
;
; GFX11-LABEL: v_mov_b64_pseudo_globaladdr:
; GFX11:       ; %bb.0: ; %entry
; GFX11-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 1, v0
; GFX11-NEXT:    v_mov_b32_e32 v0, 0
; GFX11-NEXT:    s_mov_b32 s0, exec_lo
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cmpx_ne_u32_e32 1, v2
; GFX11-NEXT:  ; %bb.1: ; %other
; GFX11-NEXT:    v_mov_b32_e32 v0, gv@abs32@lo
; GFX11-NEXT:    v_mov_b32_e32 v1, gv@abs32@hi
; GFX11-NEXT:  ; %bb.2: ; %join
; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
; GFX11-NEXT:    v_readfirstlane_b32 s1, v1
; GFX11-NEXT:    ; return to shader part epilog
entry:
  br i1 %cond, label %join, label %other

other:
  br label %join

join:
  %sink = phi ptr addrspace(4) [ null, %entry ], [ @gv, %other ]
  ret ptr addrspace(4) %sink
}

; Uniform select of @gv lowers to S_MOV_B64_IMM_PSEUDO with a GlobalAddress
; operand which expandPostRAPseudo splits into s_mov_b32 abs32@lo/@hi.
define amdgpu_ps ptr addrspace(4) @s_mov_b64_imm_pseudo_globaladdr(i1 inreg %cond) {
; GFX10-LABEL: s_mov_b64_imm_pseudo_globaladdr:
; GFX10:       ; %bb.0: ; %entry
; GFX10-NEXT:    s_bitcmp1_b32 s0, 0
; GFX10-NEXT:    s_cselect_b32 s0, -1, 0
; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s0
; GFX10-NEXT:    s_mov_b64 s[0:1], 0
; GFX10-NEXT:    s_cbranch_vccnz .LBB1_2
; GFX10-NEXT:  ; %bb.1: ; %other
; GFX10-NEXT:    s_mov_b32 s1, gv@abs32@hi
; GFX10-NEXT:    s_mov_b32 s0, gv@abs32@lo
; GFX10-NEXT:  .LBB1_2: ; %join
; GFX10-NEXT:    ; return to shader part epilog
;
; GFX11-LABEL: s_mov_b64_imm_pseudo_globaladdr:
; GFX11:       ; %bb.0: ; %entry
; GFX11-NEXT:    s_bitcmp1_b32 s0, 0
; GFX11-NEXT:    s_cselect_b32 s0, -1, 0
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s0
; GFX11-NEXT:    s_mov_b64 s[0:1], 0
; GFX11-NEXT:    s_cbranch_vccnz .LBB1_2
; GFX11-NEXT:  ; %bb.1: ; %other
; GFX11-NEXT:    s_mov_b32 s1, gv@abs32@hi
; GFX11-NEXT:    s_mov_b32 s0, gv@abs32@lo
; GFX11-NEXT:  .LBB1_2: ; %join
; GFX11-NEXT:    ; return to shader part epilog
entry:
  br i1 %cond, label %join, label %other

other:
  br label %join

join:
  %sink = phi ptr addrspace(4) [ null, %entry ], [ @gv, %other ]
  ret ptr addrspace(4) %sink
}