llvm/test/CodeGen/AMDGPU/anyext-s16-to-s64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck %s --check-prefix=SDAG-FAKE16
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -mattr=-real-true16 < %s | FileCheck %s --check-prefix=GISEL-FAKE16
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck %s --check-prefix=SDAG-TRUE16
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -mattr=+real-true16 < %s | FileCheck %s --check-prefix=GISEL-TRUE16

; idx for swmmac is extended via anyext from i16 to i64.
define amdgpu_ps void @test_swmmac_f32_16x16x128_fp8_fp8_i16_index(<8 x i32> %a, <16 x i32> %b, <8 x float> %c, ptr addrspace(1) %idx.ptr, ptr addrspace(1) %out) {
; SDAG-FAKE16-LABEL: test_swmmac_f32_16x16x128_fp8_fp8_i16_index:
; SDAG-FAKE16:       ; %bb.0:
; SDAG-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; SDAG-FAKE16-NEXT:    v_nop
; SDAG-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-FAKE16-NEXT:    global_load_u16 v32, v[32:33], off
; SDAG-FAKE16-NEXT:    s_wait_xcnt 0x0
; SDAG-FAKE16-NEXT:    v_mov_b32_e32 v33, 0
; SDAG-FAKE16-NEXT:    s_wait_loadcnt 0x0
; SDAG-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; SDAG-FAKE16-NEXT:    v_swmmac_f32_16x16x128_fp8_fp8 v[24:31], v[0:7], v[8:23], v[32:33]
; SDAG-FAKE16-NEXT:    s_clause 0x1
; SDAG-FAKE16-NEXT:    global_store_b128 v[34:35], v[28:31], off offset:16
; SDAG-FAKE16-NEXT:    global_store_b128 v[34:35], v[24:27], off
; SDAG-FAKE16-NEXT:    s_endpgm
;
; GISEL-FAKE16-LABEL: test_swmmac_f32_16x16x128_fp8_fp8_i16_index:
; GISEL-FAKE16:       ; %bb.0:
; GISEL-FAKE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GISEL-FAKE16-NEXT:    v_nop
; GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-FAKE16-NEXT:    global_load_u16 v32, v[32:33], off
; GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
; GISEL-FAKE16-NEXT:    v_swmmac_f32_16x16x128_fp8_fp8 v[24:31], v[0:7], v[8:23], v[32:33]
; GISEL-FAKE16-NEXT:    s_clause 0x1
; GISEL-FAKE16-NEXT:    global_store_b128 v[34:35], v[24:27], off
; GISEL-FAKE16-NEXT:    global_store_b128 v[34:35], v[28:31], off offset:16
; GISEL-FAKE16-NEXT:    s_endpgm
;
; SDAG-TRUE16-LABEL: test_swmmac_f32_16x16x128_fp8_fp8_i16_index:
; SDAG-TRUE16:       ; %bb.0:
; SDAG-TRUE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; SDAG-TRUE16-NEXT:    v_nop
; SDAG-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-TRUE16-NEXT:    global_load_u16 v32, v[32:33], off
; SDAG-TRUE16-NEXT:    s_wait_loadcnt 0x0
; SDAG-TRUE16-NEXT:    v_swmmac_f32_16x16x128_fp8_fp8 v[24:31], v[0:7], v[8:23], v[32:33]
; SDAG-TRUE16-NEXT:    s_clause 0x1
; SDAG-TRUE16-NEXT:    global_store_b128 v[34:35], v[28:31], off offset:16
; SDAG-TRUE16-NEXT:    global_store_b128 v[34:35], v[24:27], off
; SDAG-TRUE16-NEXT:    s_endpgm
;
; GISEL-TRUE16-LABEL: test_swmmac_f32_16x16x128_fp8_fp8_i16_index:
; GISEL-TRUE16:       ; %bb.0:
; GISEL-TRUE16-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GISEL-TRUE16-NEXT:    v_nop
; GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-TRUE16-NEXT:    global_load_u16 v32, v[32:33], off
; GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
; GISEL-TRUE16-NEXT:    v_swmmac_f32_16x16x128_fp8_fp8 v[24:31], v[0:7], v[8:23], v[32:33]
; GISEL-TRUE16-NEXT:    s_clause 0x1
; GISEL-TRUE16-NEXT:    global_store_b128 v[34:35], v[24:27], off
; GISEL-TRUE16-NEXT:    global_store_b128 v[34:35], v[28:31], off offset:16
; GISEL-TRUE16-NEXT:    s_endpgm
  %idx = load i16, ptr addrspace(1) %idx.ptr, align 2
  %res = call <8 x float> @llvm.amdgcn.swmmac.f32.16x16x128.fp8.fp8.v8f32.v8i32.v16i32.i16(<8 x i32> %a, <16 x i32> %b, <8 x float> %c, i16 %idx, i1 false, i1 false)
  store <8 x float> %res, ptr addrspace(1) %out
  ret void
}

declare <8 x float> @llvm.amdgcn.swmmac.f32.16x16x128.fp8.fp8.v8f32.v8i32.v16i32.i16(<8 x i32>, <16 x i32>, <8 x float>, i16, i1 immarg, i1 immarg)