llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgpu9.42-amd-amdhsa < %s | FileCheck -check-prefixes=GFX942,GFX942-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu9.42-amd-amdhsa < %s | FileCheck -check-prefixes=GFX942,GFX942-GISEL %s

; RUN: llc -global-isel=0 -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck -check-prefixes=GFX1030,GFX1030-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu10.30-amd-amdhsa < %s | FileCheck -check-prefixes=GFX1030,GFX1030-GISEL %s

; RUN: llc -global-isel=0 -mtriple=amdgpu12.00-amd-amdhsa < %s | FileCheck -check-prefixes=GFX1200,GFX1200-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.00-amd-amdhsa < %s | FileCheck -check-prefixes=GFX1200,GFX1200-GISEL %s

; RUN: llc -global-isel=0 -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s

@bar = internal addrspace(15) global target("amdgcn.named.barrier", 0) poison

define amdgpu_kernel void @barrier_to_generic(ptr addrspace(15) %bar, ptr %out) {
; GFX942-SDAG-LABEL: barrier_to_generic:
; GFX942-SDAG:       ; %bb.0:
; GFX942-SDAG-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX942-SDAG-NEXT:    s_load_dword s0, s[4:5], 0x0
; GFX942-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x8
; GFX942-SDAG-NEXT:    s_or_b32 s1, s1, 1
; GFX942-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT:    s_cmp_lg_u32 s0, 0
; GFX942-SDAG-NEXT:    s_cselect_b32 s1, s1, 0
; GFX942-SDAG-NEXT:    s_cselect_b32 s0, s0, 0
; GFX942-SDAG-NEXT:    v_mov_b32_e32 v2, s0
; GFX942-SDAG-NEXT:    v_mov_b32_e32 v3, s1
; GFX942-SDAG-NEXT:    v_mov_b64_e32 v[0:1], s[2:3]
; GFX942-SDAG-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
; GFX942-SDAG-NEXT:    s_endpgm
;
; GFX942-GISEL-LABEL: barrier_to_generic:
; GFX942-GISEL:       ; %bb.0:
; GFX942-GISEL-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX942-GISEL-NEXT:    s_load_dword s0, s[4:5], 0x0
; GFX942-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x8
; GFX942-GISEL-NEXT:    s_or_b32 s1, s1, 1
; GFX942-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX942-GISEL-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
; GFX942-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GFX942-GISEL-NEXT:    s_endpgm
;
; GFX1030-SDAG-LABEL: barrier_to_generic:
; GFX1030-SDAG:       ; %bb.0:
; GFX1030-SDAG-NEXT:    s_add_u32 s12, s12, s17
; GFX1030-SDAG-NEXT:    s_addc_u32 s13, s13, 0
; GFX1030-SDAG-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1030-SDAG-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1030-SDAG-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1030-SDAG-NEXT:    s_clause 0x1
; GFX1030-SDAG-NEXT:    s_load_dword s0, s[8:9], 0x0
; GFX1030-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x8
; GFX1030-SDAG-NEXT:    s_or_b32 s1, s1, 1
; GFX1030-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX1030-SDAG-NEXT:    s_cmp_lg_u32 s0, 0
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v2, s2
; GFX1030-SDAG-NEXT:    s_cselect_b32 s0, s0, 0
; GFX1030-SDAG-NEXT:    s_cselect_b32 s1, s1, 0
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v1, s1
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v3, s3
; GFX1030-SDAG-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GFX1030-SDAG-NEXT:    s_endpgm
;
; GFX1030-GISEL-LABEL: barrier_to_generic:
; GFX1030-GISEL:       ; %bb.0:
; GFX1030-GISEL-NEXT:    s_add_u32 s12, s12, s17
; GFX1030-GISEL-NEXT:    s_addc_u32 s13, s13, 0
; GFX1030-GISEL-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1030-GISEL-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1030-GISEL-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1030-GISEL-NEXT:    s_clause 0x1
; GFX1030-GISEL-NEXT:    s_load_dword s0, s[8:9], 0x0
; GFX1030-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x8
; GFX1030-GISEL-NEXT:    s_or_b32 s1, s1, 1
; GFX1030-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX1030-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v2, s2
; GFX1030-GISEL-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v3, s3
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v1, s1
; GFX1030-GISEL-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GFX1030-GISEL-NEXT:    s_endpgm
;
; GFX1200-SDAG-LABEL: barrier_to_generic:
; GFX1200-SDAG:       ; %bb.0:
; GFX1200-SDAG-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1200-SDAG-NEXT:    s_clause 0x1
; GFX1200-SDAG-NEXT:    s_load_b32 s0, s[4:5], 0x0
; GFX1200-SDAG-NEXT:    s_load_b64 s[2:3], s[4:5], 0x8
; GFX1200-SDAG-NEXT:    s_or_b32 s1, s1, 1
; GFX1200-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1200-SDAG-NEXT:    s_cmp_lg_u32 s0, 0
; GFX1200-SDAG-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX1200-SDAG-NEXT:    s_cselect_b32 s0, s0, 0
; GFX1200-SDAG-NEXT:    s_cselect_b32 s1, s1, 0
; GFX1200-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-SDAG-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX1200-SDAG-NEXT:    flat_store_b64 v[2:3], v[0:1]
; GFX1200-SDAG-NEXT:    s_endpgm
;
; GFX1200-GISEL-LABEL: barrier_to_generic:
; GFX1200-GISEL:       ; %bb.0:
; GFX1200-GISEL-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1200-GISEL-NEXT:    s_clause 0x1
; GFX1200-GISEL-NEXT:    s_load_b32 s0, s[4:5], 0x0
; GFX1200-GISEL-NEXT:    s_load_b64 s[2:3], s[4:5], 0x8
; GFX1200-GISEL-NEXT:    s_or_b32 s1, s1, 1
; GFX1200-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1200-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX1200-GISEL-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX1200-GISEL-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
; GFX1200-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX1200-GISEL-NEXT:    flat_store_b64 v[2:3], v[0:1]
; GFX1200-GISEL-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: barrier_to_generic:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1250-SDAG-NEXT:    s_clause 0x1
; GFX1250-SDAG-NEXT:    s_load_b32 s0, s[4:5], 0x0 nv
; GFX1250-SDAG-NEXT:    s_load_b64 s[2:3], s[4:5], 0x8 nv
; GFX1250-SDAG-NEXT:    s_or_b32 s1, s1, 1
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    s_cmp_lg_u32 s0, 0
; GFX1250-SDAG-NEXT:    s_cselect_b32 s0, s0, 0
; GFX1250-SDAG-NEXT:    s_cselect_b32 s1, s1, 0
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, s0
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v1, s1
; GFX1250-SDAG-NEXT:    flat_store_b64 v2, v[0:1], s[2:3]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: barrier_to_generic:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1250-GISEL-NEXT:    s_clause 0x1
; GFX1250-GISEL-NEXT:    s_load_b32 s0, s[4:5], 0x0 nv
; GFX1250-GISEL-NEXT:    s_load_b64 s[2:3], s[4:5], 0x8 nv
; GFX1250-GISEL-NEXT:    s_or_b32 s1, s1, 1
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v2, 0
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    s_cmp_lg_u32 s0, 0
; GFX1250-GISEL-NEXT:    s_cselect_b64 s[0:1], s[0:1], 0
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
; GFX1250-GISEL-NEXT:    flat_store_b64 v2, v[0:1], s[2:3]
; GFX1250-GISEL-NEXT:    s_endpgm
  %res = addrspacecast ptr addrspace(15) %bar to ptr
  store ptr %res, ptr %out
  ret void
}

define amdgpu_kernel void @barrier_gv_to_generic(ptr %out) {
; GFX942-SDAG-LABEL: barrier_gv_to_generic:
; GFX942-SDAG:       ; %bb.0:
; GFX942-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x0
; GFX942-SDAG-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX942-SDAG-NEXT:    s_or_b32 s0, s1, 1
; GFX942-SDAG-NEXT:    v_mov_b32_e32 v2, 1
; GFX942-SDAG-NEXT:    v_mov_b32_e32 v3, s0
; GFX942-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT:    v_mov_b64_e32 v[0:1], s[2:3]
; GFX942-SDAG-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
; GFX942-SDAG-NEXT:    s_endpgm
;
; GFX942-GISEL-LABEL: barrier_gv_to_generic:
; GFX942-GISEL:       ; %bb.0:
; GFX942-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x0
; GFX942-GISEL-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX942-GISEL-NEXT:    s_mov_b32 s0, 1
; GFX942-GISEL-NEXT:    s_or_b32 s1, s1, 1
; GFX942-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
; GFX942-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT:    v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-GISEL-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GFX942-GISEL-NEXT:    s_endpgm
;
; GFX1030-SDAG-LABEL: barrier_gv_to_generic:
; GFX1030-SDAG:       ; %bb.0:
; GFX1030-SDAG-NEXT:    s_add_u32 s12, s12, s17
; GFX1030-SDAG-NEXT:    s_addc_u32 s13, s13, 0
; GFX1030-SDAG-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1030-SDAG-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1030-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x0
; GFX1030-SDAG-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v0, 1
; GFX1030-SDAG-NEXT:    s_or_b32 s0, s1, 1
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v1, s0
; GFX1030-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v2, s2
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v3, s3
; GFX1030-SDAG-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GFX1030-SDAG-NEXT:    s_endpgm
;
; GFX1030-GISEL-LABEL: barrier_gv_to_generic:
; GFX1030-GISEL:       ; %bb.0:
; GFX1030-GISEL-NEXT:    s_add_u32 s12, s12, s17
; GFX1030-GISEL-NEXT:    s_addc_u32 s13, s13, 0
; GFX1030-GISEL-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1030-GISEL-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1030-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x0
; GFX1030-GISEL-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1030-GISEL-NEXT:    s_mov_b32 s0, 1
; GFX1030-GISEL-NEXT:    s_or_b32 s1, s1, 1
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v1, s1
; GFX1030-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v2, s2
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v3, s3
; GFX1030-GISEL-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GFX1030-GISEL-NEXT:    s_endpgm
;
; GFX1200-SDAG-LABEL: barrier_gv_to_generic:
; GFX1200-SDAG:       ; %bb.0:
; GFX1200-SDAG-NEXT:    s_load_b64 s[2:3], s[4:5], 0x0
; GFX1200-SDAG-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1200-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1200-SDAG-NEXT:    s_or_b32 s0, s1, 1
; GFX1200-SDAG-NEXT:    v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, s0
; GFX1200-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1200-SDAG-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX1200-SDAG-NEXT:    flat_store_b64 v[2:3], v[0:1]
; GFX1200-SDAG-NEXT:    s_endpgm
;
; GFX1200-GISEL-LABEL: barrier_gv_to_generic:
; GFX1200-GISEL:       ; %bb.0:
; GFX1200-GISEL-NEXT:    s_load_b64 s[2:3], s[4:5], 0x0
; GFX1200-GISEL-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1200-GISEL-NEXT:    s_mov_b32 s0, 1
; GFX1200-GISEL-NEXT:    s_or_b32 s1, s1, 1
; GFX1200-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX1200-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1200-GISEL-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX1200-GISEL-NEXT:    flat_store_b64 v[2:3], v[0:1]
; GFX1200-GISEL-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: barrier_gv_to_generic:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    s_load_b64 s[2:3], s[4:5], 0x0 nv
; GFX1250-SDAG-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v0, 1
; GFX1250-SDAG-NEXT:    s_or_b32 s0, s1, 1
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v1, s0
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    flat_store_b64 v2, v[0:1], s[2:3]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: barrier_gv_to_generic:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    s_load_b64 s[2:3], s[4:5], 0x0 nv
; GFX1250-GISEL-NEXT:    s_mov_b64 s[0:1], src_shared_base
; GFX1250-GISEL-NEXT:    s_mov_b32 s0, 1
; GFX1250-GISEL-NEXT:    s_or_b32 s1, s1, 1
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v2, 0
; GFX1250-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    flat_store_b64 v2, v[0:1], s[2:3]
; GFX1250-GISEL-NEXT:    s_endpgm
  %res = addrspacecast ptr addrspace(15) @bar to ptr
  store ptr %res, ptr %out
  ret void
}


define amdgpu_kernel void @barrier_null_to_generic(ptr %out) {
; GFX942-LABEL: barrier_null_to_generic:
; GFX942:       ; %bb.0:
; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX942-NEXT:    v_mov_b64_e32 v[0:1], 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    v_mov_b64_e32 v[2:3], s[0:1]
; GFX942-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GFX942-NEXT:    s_endpgm
;
; GFX1030-SDAG-LABEL: barrier_null_to_generic:
; GFX1030-SDAG:       ; %bb.0:
; GFX1030-SDAG-NEXT:    s_add_u32 s12, s12, s17
; GFX1030-SDAG-NEXT:    s_addc_u32 s13, s13, 0
; GFX1030-SDAG-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1030-SDAG-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1030-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v1, v0
; GFX1030-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v3, s1
; GFX1030-SDAG-NEXT:    v_mov_b32_e32 v2, s0
; GFX1030-SDAG-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GFX1030-SDAG-NEXT:    s_endpgm
;
; GFX1030-GISEL-LABEL: barrier_null_to_generic:
; GFX1030-GISEL:       ; %bb.0:
; GFX1030-GISEL-NEXT:    s_add_u32 s12, s12, s17
; GFX1030-GISEL-NEXT:    s_addc_u32 s13, s13, 0
; GFX1030-GISEL-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1030-GISEL-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1030-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v0, 0
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX1030-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v3, s1
; GFX1030-GISEL-NEXT:    v_mov_b32_e32 v2, s0
; GFX1030-GISEL-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GFX1030-GISEL-NEXT:    s_endpgm
;
; GFX1200-SDAG-LABEL: barrier_null_to_generic:
; GFX1200-SDAG:       ; %bb.0:
; GFX1200-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
; GFX1200-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1200-SDAG-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, s1
; GFX1200-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1200-SDAG-NEXT:    v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, s0
; GFX1200-SDAG-NEXT:    flat_store_b64 v[2:3], v[0:1]
; GFX1200-SDAG-NEXT:    s_endpgm
;
; GFX1200-GISEL-LABEL: barrier_null_to_generic:
; GFX1200-GISEL:       ; %bb.0:
; GFX1200-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
; GFX1200-GISEL-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX1200-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1200-GISEL-NEXT:    v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX1200-GISEL-NEXT:    flat_store_b64 v[2:3], v[0:1]
; GFX1200-GISEL-NEXT:    s_endpgm
;
; GFX1250-LABEL: barrier_null_to_generic:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GFX1250-NEXT:    v_mov_b64_e32 v[0:1], 0
; GFX1250-NEXT:    v_mov_b32_e32 v2, 0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    flat_store_b64 v2, v[0:1], s[0:1]
; GFX1250-NEXT:    s_endpgm
  %res = addrspacecast ptr addrspace(15) null to ptr
  store ptr %res, ptr %out
  ret void
}

define amdgpu_kernel void @generic_to_barrier(ptr %generic, ptr %out) {
; GFX942-SDAG-LABEL: generic_to_barrier:
; GFX942-SDAG:       ; %bb.0:
; GFX942-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX942-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-SDAG-NEXT:    s_cmp_lg_u64 s[0:1], 0
; GFX942-SDAG-NEXT:    s_cselect_b32 s0, s0, 0
; GFX942-SDAG-NEXT:    v_mov_b32_e32 v0, s2
; GFX942-SDAG-NEXT:    v_mov_b32_e32 v1, s3
; GFX942-SDAG-NEXT:    v_mov_b32_e32 v2, s0
; GFX942-SDAG-NEXT:    flat_store_dword v[0:1], v2
; GFX942-SDAG-NEXT:    s_endpgm
;
; GFX942-GISEL-LABEL: generic_to_barrier:
; GFX942-GISEL:       ; %bb.0:
; GFX942-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX942-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-GISEL-NEXT:    s_cmp_lg_u64 s[0:1], 0
; GFX942-GISEL-NEXT:    s_cselect_b32 s0, s0, 0
; GFX942-GISEL-NEXT:    v_mov_b32_e32 v2, s0
; GFX942-GISEL-NEXT:    v_mov_b64_e32 v[0:1], s[2:3]
; GFX942-GISEL-NEXT:    flat_store_dword v[0:1], v2
; GFX942-GISEL-NEXT:    s_endpgm
;
; GFX1030-LABEL: generic_to_barrier:
; GFX1030:       ; %bb.0:
; GFX1030-NEXT:    s_add_u32 s12, s12, s17
; GFX1030-NEXT:    s_addc_u32 s13, s13, 0
; GFX1030-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1030-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1030-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX1030-NEXT:    s_waitcnt lgkmcnt(0)
; GFX1030-NEXT:    s_cmp_lg_u64 s[0:1], 0
; GFX1030-NEXT:    v_mov_b32_e32 v0, s2
; GFX1030-NEXT:    s_cselect_b32 s0, s0, 0
; GFX1030-NEXT:    v_mov_b32_e32 v1, s3
; GFX1030-NEXT:    v_mov_b32_e32 v2, s0
; GFX1030-NEXT:    flat_store_dword v[0:1], v2
; GFX1030-NEXT:    s_endpgm
;
; GFX1200-SDAG-LABEL: generic_to_barrier:
; GFX1200-SDAG:       ; %bb.0:
; GFX1200-SDAG-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX1200-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1200-SDAG-NEXT:    s_cmp_lg_u64 s[0:1], 0
; GFX1200-SDAG-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX1200-SDAG-NEXT:    s_cselect_b32 s0, s0, 0
; GFX1200-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-SDAG-NEXT:    v_mov_b32_e32 v2, s0
; GFX1200-SDAG-NEXT:    flat_store_b32 v[0:1], v2
; GFX1200-SDAG-NEXT:    s_endpgm
;
; GFX1200-GISEL-LABEL: generic_to_barrier:
; GFX1200-GISEL:       ; %bb.0:
; GFX1200-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX1200-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1200-GISEL-NEXT:    s_cmp_lg_u64 s[0:1], 0
; GFX1200-GISEL-NEXT:    v_mov_b32_e32 v0, s2
; GFX1200-GISEL-NEXT:    s_cselect_b32 s0, s0, 0
; GFX1200-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-GISEL-NEXT:    v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s0
; GFX1200-GISEL-NEXT:    flat_store_b32 v[0:1], v2
; GFX1200-GISEL-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: generic_to_barrier:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    s_cmp_lg_u64 s[0:1], 0
; GFX1250-SDAG-NEXT:    s_cselect_b32 s0, s0, 0
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX1250-SDAG-NEXT:    flat_store_b32 v0, v1, s[2:3]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: generic_to_barrier:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    s_cmp_lg_u64 s[0:1], 0
; GFX1250-GISEL-NEXT:    s_cselect_b32 s0, s0, 0
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX1250-GISEL-NEXT:    flat_store_b32 v1, v0, s[2:3]
; GFX1250-GISEL-NEXT:    s_endpgm
  %res = addrspacecast ptr %generic to ptr addrspace(15)
  store ptr addrspace(15) %res, ptr %out
  ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1200: {{.*}}