llvm/test/CodeGen/AArch64/umulh.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI

define i16 @umulh_i16(i16 %x, i16 %y) nounwind {
; CHECK-SD-LABEL: umulh_i16:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    and w8, w1, #0xffff
; CHECK-SD-NEXT:    and w9, w0, #0xffff
; CHECK-SD-NEXT:    mul w8, w9, w8
; CHECK-SD-NEXT:    lsr w0, w8, #16
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: umulh_i16:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    and w8, w0, #0xffff
; CHECK-GI-NEXT:    and w9, w1, #0xffff
; CHECK-GI-NEXT:    mul w8, w8, w9
; CHECK-GI-NEXT:    lsr w0, w8, #16
; CHECK-GI-NEXT:    ret
  %r = call i16 @llvm.umulh(i16 %x, i16 %y)
  ret i16 %r
}

define i32 @umulh_i32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: umulh_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umull x8, w0, w1
; CHECK-NEXT:    lsr x0, x8, #32
; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
; CHECK-NEXT:    ret
  %r = call i32 @llvm.umulh(i32 %x, i32 %y)
  ret i32 %r
}

define i64 @umulh_i64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: umulh_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umulh x0, x0, x1
; CHECK-NEXT:    ret
  %r = call i64 @llvm.umulh(i64 %x, i64 %y)
  ret i64 %r
}

define i96 @umulh_i96(i96 %x, i96 %y) nounwind {
; CHECK-SD-LABEL: umulh_i96:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    extr x9, x1, x0, #32
; CHECK-SD-NEXT:    lsl x10, x0, #32
; CHECK-SD-NEXT:    mov w8, w3
; CHECK-SD-NEXT:    umulh x12, x10, x2
; CHECK-SD-NEXT:    mul x13, x9, x2
; CHECK-SD-NEXT:    umulh x11, x9, x2
; CHECK-SD-NEXT:    umulh x14, x10, x8
; CHECK-SD-NEXT:    mul x10, x10, x8
; CHECK-SD-NEXT:    mul x15, x9, x8
; CHECK-SD-NEXT:    umulh x8, x9, x8
; CHECK-SD-NEXT:    adds x9, x13, x12
; CHECK-SD-NEXT:    cinc x11, x11, hs
; CHECK-SD-NEXT:    cmn x10, x9
; CHECK-SD-NEXT:    adcs x9, x11, x14
; CHECK-SD-NEXT:    cset w10, hs
; CHECK-SD-NEXT:    adds x0, x15, x9
; CHECK-SD-NEXT:    adc x1, x8, x10
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: umulh_i96:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    mov w9, w3
; CHECK-GI-NEXT:    mov w11, w1
; CHECK-GI-NEXT:    umulh x8, x0, x2
; CHECK-GI-NEXT:    mul x10, x0, x9
; CHECK-GI-NEXT:    umulh x12, x11, x2
; CHECK-GI-NEXT:    umulh x13, x0, x9
; CHECK-GI-NEXT:    adds x8, x8, x10
; CHECK-GI-NEXT:    mul x14, x11, x2
; CHECK-GI-NEXT:    add x10, x12, x13
; CHECK-GI-NEXT:    umaddl x9, w11, w9, x10
; CHECK-GI-NEXT:    cset w10, hs
; CHECK-GI-NEXT:    adds x8, x8, x14
; CHECK-GI-NEXT:    and x10, x10, #0x1
; CHECK-GI-NEXT:    cset w11, hs
; CHECK-GI-NEXT:    add x9, x9, x10
; CHECK-GI-NEXT:    and x11, x11, #0x1
; CHECK-GI-NEXT:    add x9, x9, x11
; CHECK-GI-NEXT:    lsr x1, x9, #32
; CHECK-GI-NEXT:    extr x0, x9, x8, #32
; CHECK-GI-NEXT:    ret
  %r = call i96 @llvm.umulh(i96 %x, i96 %y)
  ret i96 %r
}

define i128 @umulh_i128(i128 %x, i128 %y) nounwind {
; CHECK-SD-LABEL: umulh_i128:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    umulh x9, x0, x2
; CHECK-SD-NEXT:    mul x10, x1, x2
; CHECK-SD-NEXT:    umulh x8, x1, x2
; CHECK-SD-NEXT:    mul x12, x0, x3
; CHECK-SD-NEXT:    adds x9, x10, x9
; CHECK-SD-NEXT:    umulh x11, x0, x3
; CHECK-SD-NEXT:    cinc x8, x8, hs
; CHECK-SD-NEXT:    mul x13, x1, x3
; CHECK-SD-NEXT:    cmn x12, x9
; CHECK-SD-NEXT:    umulh x10, x1, x3
; CHECK-SD-NEXT:    cinc x9, x11, hs
; CHECK-SD-NEXT:    adds x8, x8, x9
; CHECK-SD-NEXT:    cset w9, hs
; CHECK-SD-NEXT:    adds x0, x13, x8
; CHECK-SD-NEXT:    adc x1, x10, x9
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: umulh_i128:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    umulh x8, x0, x2
; CHECK-GI-NEXT:    mul x9, x0, x3
; CHECK-GI-NEXT:    mul x10, x1, x2
; CHECK-GI-NEXT:    umulh x11, x1, x2
; CHECK-GI-NEXT:    adds x8, x8, x9
; CHECK-GI-NEXT:    umulh x12, x0, x3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    cmn x8, x10
; CHECK-GI-NEXT:    and x9, x9, #0x1
; CHECK-GI-NEXT:    mul x13, x1, x3
; CHECK-GI-NEXT:    cset w10, hs
; CHECK-GI-NEXT:    and x10, x10, #0x1
; CHECK-GI-NEXT:    umulh x14, x2, xzr
; CHECK-GI-NEXT:    add x9, x9, x10
; CHECK-GI-NEXT:    adds x11, x11, x12
; CHECK-GI-NEXT:    umulh x8, x1, x3
; CHECK-GI-NEXT:    cset w10, hs
; CHECK-GI-NEXT:    adds x11, x11, x13
; CHECK-GI-NEXT:    umulh x12, x0, xzr
; CHECK-GI-NEXT:    cset w13, hs
; CHECK-GI-NEXT:    adds x0, x11, x9
; CHECK-GI-NEXT:    and x9, x10, #0x1
; CHECK-GI-NEXT:    and x10, x13, #0x1
; CHECK-GI-NEXT:    cset w11, hs
; CHECK-GI-NEXT:    add x9, x9, x10
; CHECK-GI-NEXT:    and x10, x11, #0x1
; CHECK-GI-NEXT:    add x8, x14, x8
; CHECK-GI-NEXT:    add x9, x9, x10
; CHECK-GI-NEXT:    add x8, x8, x12
; CHECK-GI-NEXT:    add x1, x8, x9
; CHECK-GI-NEXT:    ret
  %r = call i128 @llvm.umulh(i128 %x, i128 %y)
  ret i128 %r
}

define <8 x i8> @umulh_v8i8(<8 x i8> %x, <8 x i8> %y) nounwind {
; CHECK-LABEL: umulh_v8i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umull v0.8h, v0.8b, v1.8b
; CHECK-NEXT:    shrn v0.8b, v0.8h, #8
; CHECK-NEXT:    ret
  %r = call <8 x i8> @llvm.umulh(<8 x i8> %x, <8 x i8> %y)
  ret <8 x i8> %r
}

define <4 x i16> @umulh_v4i16(<4 x i16> %x, <4 x i16> %y) nounwind {
; CHECK-LABEL: umulh_v4i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umull v0.4s, v0.4h, v1.4h
; CHECK-NEXT:    shrn v0.4h, v0.4s, #16
; CHECK-NEXT:    ret
  %r = call <4 x i16> @llvm.umulh(<4 x i16> %x, <4 x i16> %y)
  ret <4 x i16> %r
}

define <2 x i32> @umulh_v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; CHECK-LABEL: umulh_v2i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umull v0.2d, v0.2s, v1.2s
; CHECK-NEXT:    shrn v0.2s, v0.2d, #32
; CHECK-NEXT:    ret
  %r = call <2 x i32> @llvm.umulh(<2 x i32> %x, <2 x i32> %y)
  ret <2 x i32> %r
}

define <1 x i64> @umulh_v1i64(<1 x i64> %x, <1 x i64> %y) nounwind {
; CHECK-SD-LABEL: umulh_v1i64:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    // kill: def $d1 killed $d1 def $q1
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    fmov x8, d1
; CHECK-SD-NEXT:    fmov x9, d0
; CHECK-SD-NEXT:    umulh x8, x9, x8
; CHECK-SD-NEXT:    fmov d0, x8
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: umulh_v1i64:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    fmov x8, d0
; CHECK-GI-NEXT:    fmov x9, d1
; CHECK-GI-NEXT:    umulh x8, x8, x9
; CHECK-GI-NEXT:    fmov d0, x8
; CHECK-GI-NEXT:    ret
  %r = call <1 x i64> @llvm.umulh(<1 x i64> %x, <1 x i64> %y)
  ret <1 x i64> %r
}

define <16 x i8> @umulh_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: umulh_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umull2 v2.8h, v0.16b, v1.16b
; CHECK-NEXT:    umull v0.8h, v0.8b, v1.8b
; CHECK-NEXT:    uzp2 v0.16b, v0.16b, v2.16b
; CHECK-NEXT:    ret
  %r = call <16 x i8> @llvm.umulh(<16 x i8> %x, <16 x i8> %y)
  ret <16 x i8> %r
}

define <8 x i16> @umulh_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; CHECK-LABEL: umulh_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umull2 v2.4s, v0.8h, v1.8h
; CHECK-NEXT:    umull v0.4s, v0.4h, v1.4h
; CHECK-NEXT:    uzp2 v0.8h, v0.8h, v2.8h
; CHECK-NEXT:    ret
  %r = call <8 x i16> @llvm.umulh(<8 x i16> %x, <8 x i16> %y)
  ret <8 x i16> %r
}

define <4 x i32> @umulh_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: umulh_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    umull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT:    umull v0.2d, v0.2s, v1.2s
; CHECK-NEXT:    uzp2 v0.4s, v0.4s, v2.4s
; CHECK-NEXT:    ret
  %r = call <4 x i32> @llvm.umulh(<4 x i32> %x, <4 x i32> %y)
  ret <4 x i32> %r
}

define <2 x i64> @umulh_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-SD-LABEL: umulh_v2i64:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    fmov x10, d1
; CHECK-SD-NEXT:    fmov x11, d0
; CHECK-SD-NEXT:    mov x8, v1.d[1]
; CHECK-SD-NEXT:    mov x9, v0.d[1]
; CHECK-SD-NEXT:    umulh x10, x11, x10
; CHECK-SD-NEXT:    umulh x8, x9, x8
; CHECK-SD-NEXT:    fmov d0, x10
; CHECK-SD-NEXT:    mov v0.d[1], x8
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: umulh_v2i64:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    fmov x10, d0
; CHECK-GI-NEXT:    fmov x11, d1
; CHECK-GI-NEXT:    mov x8, v0.d[1]
; CHECK-GI-NEXT:    mov x9, v1.d[1]
; CHECK-GI-NEXT:    umulh x10, x10, x11
; CHECK-GI-NEXT:    umulh x8, x8, x9
; CHECK-GI-NEXT:    fmov d0, x10
; CHECK-GI-NEXT:    mov v0.d[1], x8
; CHECK-GI-NEXT:    ret
  %r = call <2 x i64> @llvm.umulh(<2 x i64> %x, <2 x i64> %y)
  ret <2 x i64> %r
}

define <3 x i32> @umulh_v3i32(<3 x i32> %x, <3 x i32> %y) nounwind {
; CHECK-SD-LABEL: umulh_v3i32:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    umull2 v2.2d, v0.4s, v1.4s
; CHECK-SD-NEXT:    umull v0.2d, v0.2s, v1.2s
; CHECK-SD-NEXT:    uzp2 v0.4s, v0.4s, v2.4s
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: umulh_v3i32:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    mov v2.s[0], v0.s[0]
; CHECK-GI-NEXT:    mov v3.s[0], v1.s[0]
; CHECK-GI-NEXT:    mov w8, v0.s[2]
; CHECK-GI-NEXT:    mov w9, v1.s[2]
; CHECK-GI-NEXT:    mov v2.s[1], v0.s[1]
; CHECK-GI-NEXT:    mov v3.s[1], v1.s[1]
; CHECK-GI-NEXT:    umull x8, w8, w9
; CHECK-GI-NEXT:    umull v2.2d, v2.2s, v3.2s
; CHECK-GI-NEXT:    lsr x8, x8, #32
; CHECK-GI-NEXT:    ushr v2.2d, v2.2d, #32
; CHECK-GI-NEXT:    mov d0, v2.d[1]
; CHECK-GI-NEXT:    fmov x10, d2
; CHECK-GI-NEXT:    fmov x9, d0
; CHECK-GI-NEXT:    fmov s0, w10
; CHECK-GI-NEXT:    mov v0.s[1], w9
; CHECK-GI-NEXT:    mov v0.s[2], w8
; CHECK-GI-NEXT:    ret
  %r = call <3 x i32> @llvm.umulh(<3 x i32> %x, <3 x i32> %y)
  ret <3 x i32> %r
}

define <2 x i48> @umulh_v2i48(<2 x i48> %x, <2 x i48> %y) nounwind {
; CHECK-SD-LABEL: umulh_v2i48:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    movi v2.2d, #0x00ffffffffffff
; CHECK-SD-NEXT:    shl v0.2d, v0.2d, #16
; CHECK-SD-NEXT:    fmov x11, d0
; CHECK-SD-NEXT:    mov x9, v0.d[1]
; CHECK-SD-NEXT:    and v1.16b, v1.16b, v2.16b
; CHECK-SD-NEXT:    fmov x10, d1
; CHECK-SD-NEXT:    mov x8, v1.d[1]
; CHECK-SD-NEXT:    umulh x10, x11, x10
; CHECK-SD-NEXT:    umulh x8, x9, x8
; CHECK-SD-NEXT:    fmov d0, x10
; CHECK-SD-NEXT:    mov v0.d[1], x8
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: umulh_v2i48:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    fmov x9, d0
; CHECK-GI-NEXT:    fmov x10, d1
; CHECK-GI-NEXT:    mov x8, v0.d[1]
; CHECK-GI-NEXT:    mov x11, v1.d[1]
; CHECK-GI-NEXT:    and x9, x9, #0xffffffffffff
; CHECK-GI-NEXT:    and x10, x10, #0xffffffffffff
; CHECK-GI-NEXT:    mul x12, x9, x10
; CHECK-GI-NEXT:    and x8, x8, #0xffffffffffff
; CHECK-GI-NEXT:    umulh x9, x9, x10
; CHECK-GI-NEXT:    and x10, x11, #0xffffffffffff
; CHECK-GI-NEXT:    mul x11, x8, x10
; CHECK-GI-NEXT:    umulh x8, x8, x10
; CHECK-GI-NEXT:    extr x9, x9, x12, #48
; CHECK-GI-NEXT:    fmov d0, x9
; CHECK-GI-NEXT:    extr x8, x8, x11, #48
; CHECK-GI-NEXT:    mov v0.d[1], x8
; CHECK-GI-NEXT:    ret
  %r = call <2 x i48> @llvm.umulh(<2 x i48> %x, <2 x i48> %y)
  ret <2 x i48> %r
}

define <2 x i128> @umulh_v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-SD-LABEL: umulh_v2i128:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    umulh x10, x0, x4
; CHECK-SD-NEXT:    mul x11, x1, x4
; CHECK-SD-NEXT:    umulh x9, x1, x4
; CHECK-SD-NEXT:    mul x13, x0, x5
; CHECK-SD-NEXT:    adds x10, x11, x10
; CHECK-SD-NEXT:    umulh x12, x0, x5
; CHECK-SD-NEXT:    cinc x9, x9, hs
; CHECK-SD-NEXT:    mul x15, x1, x5
; CHECK-SD-NEXT:    cmn x13, x10
; CHECK-SD-NEXT:    umulh x14, x1, x5
; CHECK-SD-NEXT:    cinc x11, x12, hs
; CHECK-SD-NEXT:    umulh x16, x2, x6
; CHECK-SD-NEXT:    adds x9, x9, x11
; CHECK-SD-NEXT:    cset w12, hs
; CHECK-SD-NEXT:    adds x0, x15, x9
; CHECK-SD-NEXT:    mul x17, x3, x6
; CHECK-SD-NEXT:    adc x1, x14, x12
; CHECK-SD-NEXT:    umulh x8, x3, x6
; CHECK-SD-NEXT:    mul x10, x2, x7
; CHECK-SD-NEXT:    adds x9, x17, x16
; CHECK-SD-NEXT:    umulh x18, x2, x7
; CHECK-SD-NEXT:    cinc x8, x8, hs
; CHECK-SD-NEXT:    mul x11, x3, x7
; CHECK-SD-NEXT:    cmn x10, x9
; CHECK-SD-NEXT:    umulh x12, x3, x7
; CHECK-SD-NEXT:    cinc x9, x18, hs
; CHECK-SD-NEXT:    adds x8, x8, x9
; CHECK-SD-NEXT:    cset w9, hs
; CHECK-SD-NEXT:    adds x2, x11, x8
; CHECK-SD-NEXT:    adc x3, x12, x9
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: umulh_v2i128:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    umulh x8, x0, x4
; CHECK-GI-NEXT:    mul x9, x0, x5
; CHECK-GI-NEXT:    mul x10, x1, x4
; CHECK-GI-NEXT:    umulh x11, x1, x4
; CHECK-GI-NEXT:    adds x8, x8, x9
; CHECK-GI-NEXT:    umulh x12, x0, x5
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    cmn x8, x10
; CHECK-GI-NEXT:    and x8, x9, #0x1
; CHECK-GI-NEXT:    mul x13, x1, x5
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and x9, x9, #0x1
; CHECK-GI-NEXT:    umulh x16, x2, x6
; CHECK-GI-NEXT:    add x8, x8, x9
; CHECK-GI-NEXT:    adds x11, x11, x12
; CHECK-GI-NEXT:    mul x17, x2, x7
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    adds x11, x11, x13
; CHECK-GI-NEXT:    and x9, x9, #0x1
; CHECK-GI-NEXT:    mul x18, x3, x6
; CHECK-GI-NEXT:    cset w13, hs
; CHECK-GI-NEXT:    adds x8, x11, x8
; CHECK-GI-NEXT:    and x13, x13, #0x1
; CHECK-GI-NEXT:    umulh x14, x4, xzr
; CHECK-GI-NEXT:    add x9, x9, x13
; CHECK-GI-NEXT:    umulh x15, x1, x5
; CHECK-GI-NEXT:    umulh x1, x3, x6
; CHECK-GI-NEXT:    umulh x10, x2, x7
; CHECK-GI-NEXT:    add x14, x14, x15
; CHECK-GI-NEXT:    mul x12, x3, x7
; CHECK-GI-NEXT:    umulh x11, x3, x7
; CHECK-GI-NEXT:    cset w3, hs
; CHECK-GI-NEXT:    adds x16, x16, x17
; CHECK-GI-NEXT:    and x13, x3, #0x1
; CHECK-GI-NEXT:    umulh x17, x0, xzr
; CHECK-GI-NEXT:    cset w0, hs
; CHECK-GI-NEXT:    cmn x16, x18
; CHECK-GI-NEXT:    add x9, x9, x13
; CHECK-GI-NEXT:    cset w16, hs
; CHECK-GI-NEXT:    and x15, x0, #0x1
; CHECK-GI-NEXT:    umulh x13, x6, xzr
; CHECK-GI-NEXT:    and x16, x16, #0x1
; CHECK-GI-NEXT:    adds x10, x1, x10
; CHECK-GI-NEXT:    add x15, x15, x16
; CHECK-GI-NEXT:    cset w16, hs
; CHECK-GI-NEXT:    adds x10, x10, x12
; CHECK-GI-NEXT:    umulh x18, x2, xzr
; CHECK-GI-NEXT:    mov x0, x8
; CHECK-GI-NEXT:    add x12, x14, x17
; CHECK-GI-NEXT:    cset w14, hs
; CHECK-GI-NEXT:    adds x2, x10, x15
; CHECK-GI-NEXT:    and x10, x16, #0x1
; CHECK-GI-NEXT:    and x14, x14, #0x1
; CHECK-GI-NEXT:    cset w15, hs
; CHECK-GI-NEXT:    add x10, x10, x14
; CHECK-GI-NEXT:    and x14, x15, #0x1
; CHECK-GI-NEXT:    add x11, x13, x11
; CHECK-GI-NEXT:    add x10, x10, x14
; CHECK-GI-NEXT:    add x1, x12, x9
; CHECK-GI-NEXT:    add x11, x11, x18
; CHECK-GI-NEXT:    add x3, x11, x10
; CHECK-GI-NEXT:    ret
  %r = call <2 x i128> @llvm.umulh(<2 x i128> %x, <2 x i128> %y)
  ret <2 x i128> %r
}