llvm/test/CodeGen/AArch64/sve-ptrue-coalesce.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64 -mattr=+sve,+sme -run-pass=aarch64-ptrue-coalesce -aarch64-enable-ptrue-coalescing -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,ENABLED
# RUN: llc -mtriple=aarch64 -mattr=+sve,+sme -passes=aarch64-ptrue-coalesce -aarch64-enable-ptrue-coalescing -o - %s | FileCheck %s --check-prefixes=CHECK,ENABLED
# RUN: llc -mtriple=aarch64 -mattr=+sve,+sme -passes=aarch64-ptrue-coalesce -aarch64-enable-ptrue-coalescing=false -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,DISABLED

---
name:            ptrue_b_replaces_ptrue_h_for_h_user
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; ENABLED-LABEL: name: ptrue_b_replaces_ptrue_h_for_h_user
    ; ENABLED: liveins: $z0, $z1
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; ENABLED-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
    ; ENABLED-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; ENABLED-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: ptrue_b_replaces_ptrue_h_for_h_user
    ; DISABLED: liveins: $z0, $z1
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; DISABLED-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
    ; DISABLED-NEXT: [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
    ; DISABLED-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; DISABLED-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; DISABLED-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_B 31, implicit $vg
    %1:ppr_3b = PTRUE_H 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_H %1, %2, %3, implicit-def dead $nzcv
    %5:ppr = CMPEQ_PPzZZ_B %0, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            keep_ptrue_h_for_b_user
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; ENABLED-LABEL: name: keep_ptrue_h_for_b_user
    ; ENABLED: liveins: $z0, $z1
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; ENABLED-NEXT: [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
    ; ENABLED-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; ENABLED-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: keep_ptrue_h_for_b_user
    ; DISABLED: liveins: $z0, $z1
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; DISABLED-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
    ; DISABLED-NEXT: [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
    ; DISABLED-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; DISABLED-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; DISABLED-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_B 31, implicit $vg
    %1:ppr_3b = PTRUE_H 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_B %1, %2, %3, implicit-def dead $nzcv
    %5:ppr = CMPEQ_PPzZZ_H %0, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            ptrue_b_replaces_and_updates_ptrue_h
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; ENABLED-LABEL: name: ptrue_b_replaces_and_updates_ptrue_h
    ; ENABLED: liveins: $z0, $z1
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; ENABLED-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
    ; ENABLED-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; ENABLED-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: ptrue_b_replaces_and_updates_ptrue_h
    ; DISABLED: liveins: $z0, $z1
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; DISABLED-NEXT: [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
    ; DISABLED-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; DISABLED-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
    ; DISABLED-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; DISABLED-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_H 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_H %0, %2, %3, implicit-def dead $nzcv
    %1:ppr_3b = PTRUE_B 31, implicit $vg
    %5:ppr = CMPEQ_PPzZZ_B %1, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            ptrue_b_replaces_ptrue_h_in_dominated_block
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  ; ENABLED-LABEL: name: ptrue_b_replaces_ptrue_h_in_dominated_block
  ; ENABLED: bb.0:
  ; ENABLED-NEXT:   successors: %bb.1(0x80000000)
  ; ENABLED-NEXT:   liveins: $z0, $z1
  ; ENABLED-NEXT: {{  $}}
  ; ENABLED-NEXT:   [[COPY:%[0-9]+]]:zpr = COPY $z0
  ; ENABLED-NEXT:   [[COPY1:%[0-9]+]]:zpr = COPY $z1
  ; ENABLED-NEXT:   [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
  ; ENABLED-NEXT:   [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
  ; ENABLED-NEXT:   B %bb.1
  ; ENABLED-NEXT: {{  $}}
  ; ENABLED-NEXT: bb.1:
  ; ENABLED-NEXT:   [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
  ; ENABLED-NEXT:   RET_ReallyLR
  ;
  ; DISABLED-LABEL: name: ptrue_b_replaces_ptrue_h_in_dominated_block
  ; DISABLED: bb.0:
  ; DISABLED-NEXT:   successors: %bb.1(0x80000000)
  ; DISABLED-NEXT:   liveins: $z0, $z1
  ; DISABLED-NEXT: {{  $}}
  ; DISABLED-NEXT:   [[COPY:%[0-9]+]]:zpr = COPY $z0
  ; DISABLED-NEXT:   [[COPY1:%[0-9]+]]:zpr = COPY $z1
  ; DISABLED-NEXT:   [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
  ; DISABLED-NEXT:   [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
  ; DISABLED-NEXT:   B %bb.1
  ; DISABLED-NEXT: {{  $}}
  ; DISABLED-NEXT: bb.1:
  ; DISABLED-NEXT:   [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
  ; DISABLED-NEXT:   [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
  ; DISABLED-NEXT:   RET_ReallyLR
  bb.0:
    successors: %bb.1
    liveins: $z0, $z1

    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_B 31, implicit $vg
    %5:ppr = CMPEQ_PPzZZ_B %0, %2, %3, implicit-def dead $nzcv
    B %bb.1

  bb.1:
    %1:ppr_3b = PTRUE_H 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_H %1, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            keep_ptrue_h_when_b_user_would_observe_extra_lanes
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; CHECK-LABEL: name: keep_ptrue_h_when_b_user_would_observe_extra_lanes
    ; CHECK: liveins: $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; CHECK-NEXT: [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_B1:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; CHECK-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_B 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_B %0, %2, %3, implicit-def dead $nzcv
    %1:ppr_3b = PTRUE_H 31, implicit $vg
    %5:ppr = CMPEQ_PPzZZ_B %1, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            keep_ptrue_s_when_d_user_cannot_be_narrowed
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
  - { id: 6, class: zpr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; CHECK-LABEL: name: keep_ptrue_s_when_d_user_cannot_be_narrowed
    ; CHECK: liveins: $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_D]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; CHECK-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:zpr = IMPLICIT_DEF
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_S:%[0-9]+]]:ppr = CMPEQ_PPzZZ_S [[PTRUE_S]], [[DEF]], [[COPY]], implicit-def dead $nzcv
    ; CHECK-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_D 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_H %0, %2, %3, implicit-def dead $nzcv
    %1:ppr_3b = PTRUE_S 31, implicit $vg
    %6:zpr = IMPLICIT_DEF
    %5:ppr = CMPEQ_PPzZZ_S %1, %6, %2, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            keep_ptrue_h_when_candidate_does_not_dominate
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
  - { id: 6, class: gpr32 }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
  - { reg: '$w0', virtual-reg: '%6' }
body:             |
  ; CHECK-LABEL: name: keep_ptrue_h_when_candidate_does_not_dominate
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $z0, $z1, $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:zpr = COPY $z0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:zpr = COPY $z1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   CBZW [[COPY2]], %bb.2
  ; CHECK-NEXT:   B %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
  ; CHECK-NEXT:   [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
  ; CHECK-NEXT:   [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
  ; CHECK-NEXT:   RET_ReallyLR
  bb.0:
    successors: %bb.2, %bb.1
    liveins: $z0, $z1, $w0

    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %6:gpr32 = COPY $w0
    CBZW %6, %bb.2
    B %bb.1

  bb.1:
    successors: %bb.2

    %0:ppr_3b = PTRUE_B 31, implicit $vg
    %5:ppr = CMPEQ_PPzZZ_B %0, %2, %3, implicit-def dead $nzcv
    B %bb.2

  bb.2:
    %1:ppr_3b = PTRUE_H 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_H %1, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            ptrue_s_replaces_ptrue_d_for_d_user
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; ENABLED-LABEL: name: ptrue_s_replaces_ptrue_d_for_d_user
    ; ENABLED: liveins: $z0, $z1
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; ENABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; ENABLED-NEXT: [[CMPEQ_PPzZZ_D:%[0-9]+]]:ppr = CMPEQ_PPzZZ_D [[PTRUE_S]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; ENABLED-NEXT: [[CMPEQ_PPzZZ_S:%[0-9]+]]:ppr = CMPEQ_PPzZZ_S [[PTRUE_S]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: ptrue_s_replaces_ptrue_d_for_d_user
    ; DISABLED: liveins: $z0, $z1
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; DISABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; DISABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; DISABLED-NEXT: [[CMPEQ_PPzZZ_D:%[0-9]+]]:ppr = CMPEQ_PPzZZ_D [[PTRUE_D]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; DISABLED-NEXT: [[CMPEQ_PPzZZ_S:%[0-9]+]]:ppr = CMPEQ_PPzZZ_S [[PTRUE_S]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; DISABLED-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_S 31, implicit $vg
    %1:ppr_3b = PTRUE_D 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_D %1, %2, %3, implicit-def dead $nzcv
    %5:ppr = CMPEQ_PPzZZ_S %0, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            keep_non_all_ptrue
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; CHECK-LABEL: name: keep_non_all_ptrue
    ; CHECK: liveins: $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 1, implicit $vg
    ; CHECK-NEXT: [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; CHECK-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_B 1, implicit $vg
    %1:ppr_3b = PTRUE_H 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_B %0, %2, %3, implicit-def dead $nzcv
    %5:ppr = CMPEQ_PPzZZ_H %1, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            keep_ptrue_s_when_existing_b_user_would_observe_extra_lanes
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: zpr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; CHECK-LABEL: name: keep_ptrue_s_when_existing_b_user_would_observe_extra_lanes
    ; CHECK: liveins: $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; CHECK-NEXT: [[ADD_ZPmZ_B:%[0-9]+]]:zpr = ADD_ZPmZ_B [[PTRUE_S]], [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[ADD_ZPmZ_B]], [[COPY1]], implicit-def dead $nzcv
    ; CHECK-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_S 31, implicit $vg
    %4:zpr = ADD_ZPmZ_B %0, %2, %3
    %1:ppr_3b = PTRUE_B 31, implicit $vg
    %5:ppr = CMPEQ_PPzZZ_B %1, %4, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            do_notcoalesce_across_vg_definitions
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; CHECK-LABEL: name: do_notcoalesce_across_vg_definitions
    ; CHECK: liveins: $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; CHECK-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
    ; CHECK-NEXT: [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; CHECK-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_B 31, implicit $vg
    %5:ppr = CMPEQ_PPzZZ_B %0, %2, %3, implicit-def dead $nzcv
    MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg
    %1:ppr_3b = PTRUE_H 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_H %1, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            constrained_ptrue_b_replaces_ptrue_h_for_h_user
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
  - { id: 6, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; ENABLED-LABEL: name: constrained_ptrue_b_replaces_ptrue_h_for_h_user
    ; ENABLED: liveins: $z0, $z1
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; ENABLED-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_3b = PTRUE_B 31, implicit $vg
    ; ENABLED-NEXT: [[BRKN_PPzP:%[0-9]+]]:ppr = BRKN_PPzP [[PTRUE_B]], [[PTRUE_B]], [[PTRUE_B]]
    ; ENABLED-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_B]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: constrained_ptrue_b_replaces_ptrue_h_for_h_user
    ; DISABLED: liveins: $z0, $z1
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; DISABLED-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
    ; DISABLED-NEXT: [[BRKN_PPzP:%[0-9]+]]:ppr = BRKN_PPzP [[PTRUE_B]], [[PTRUE_B]], [[PTRUE_B]]
    ; DISABLED-NEXT: [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
    ; DISABLED-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; DISABLED-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr = PTRUE_B 31, implicit $vg
    %6:ppr = BRKN_PPzP %0, %0, %0
    %1:ppr_3b = PTRUE_H 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_H %1, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            keep_ptrue_when_constrain_regclass_fails
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_p8to15 }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
  - { id: 6, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; CHECK-LABEL: name: keep_ptrue_when_constrain_regclass_fails
    ; CHECK: liveins: $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr_p8to15 = PTRUE_B 31, implicit $vg
    ; CHECK-NEXT: [[BRKN_PPzP:%[0-9]+]]:ppr = BRKN_PPzP [[PTRUE_B]], [[PTRUE_B]], [[PTRUE_B]]
    ; CHECK-NEXT: [[PTRUE_H:%[0-9]+]]:ppr_3b = PTRUE_H 31, implicit $vg
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[PTRUE_H]], [[COPY]], [[COPY1]], implicit-def dead $nzcv
    ; CHECK-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_p8to15 = PTRUE_B 31, implicit $vg
    %6:ppr = BRKN_PPzP %0, %0, %0
    %1:ppr_3b = PTRUE_H 31, implicit $vg
    %4:ppr = CMPEQ_PPzZZ_H %1, %2, %3, implicit-def dead $nzcv
    RET_ReallyLR

...
---
name:            ptrue_s_replaces_ptrue_d_for_d_user_fcmp
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; ENABLED-LABEL: name: ptrue_s_replaces_ptrue_d_for_d_user_fcmp
    ; ENABLED: liveins: $z0, $z1
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; ENABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; ENABLED-NEXT: [[FCMNE_PPzZZ_D:%[0-9]+]]:ppr = nofpexcept FCMNE_PPzZZ_D [[PTRUE_S]], [[COPY]], [[COPY1]]
    ; ENABLED-NEXT: [[FCMNE_PPzZZ_D1:%[0-9]+]]:ppr = nofpexcept FCMNE_PPzZZ_D [[PTRUE_S]], [[COPY]], [[COPY1]]
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: ptrue_s_replaces_ptrue_d_for_d_user_fcmp
    ; DISABLED: liveins: $z0, $z1
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; DISABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; DISABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; DISABLED-NEXT: [[FCMNE_PPzZZ_D:%[0-9]+]]:ppr = nofpexcept FCMNE_PPzZZ_D [[PTRUE_D]], [[COPY]], [[COPY1]]
    ; DISABLED-NEXT: [[FCMNE_PPzZZ_D1:%[0-9]+]]:ppr = nofpexcept FCMNE_PPzZZ_D [[PTRUE_S]], [[COPY]], [[COPY1]]
    ; DISABLED-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_S 31, implicit $vg
    %1:ppr_3b = PTRUE_D 31, implicit $vg
    %4:ppr = nofpexcept FCMNE_PPzZZ_D %1, %2, %3
    %5:ppr = nofpexcept FCMNE_PPzZZ_D %0, %2, %3
    RET_ReallyLR

...
---
name:            ptrue_s_replaces_ptrue_d_for_d_user_fcmpz
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: zpr }
  - { id: 3, class: zpr }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
liveins:
  - { reg: '$z0', virtual-reg: '%2' }
  - { reg: '$z1', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $z0, $z1

    ; ENABLED-LABEL: name: ptrue_s_replaces_ptrue_d_for_d_user_fcmpz
    ; ENABLED: liveins: $z0, $z1
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; ENABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; ENABLED-NEXT: [[FCMNE_PPzZ0_D:%[0-9]+]]:ppr = nofpexcept FCMNE_PPzZ0_D [[PTRUE_S]], [[COPY]]
    ; ENABLED-NEXT: [[FCMNE_PPzZ0_D1:%[0-9]+]]:ppr = nofpexcept FCMNE_PPzZ0_D [[PTRUE_S]], [[COPY1]]
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: ptrue_s_replaces_ptrue_d_for_d_user_fcmpz
    ; DISABLED: liveins: $z0, $z1
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; DISABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; DISABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; DISABLED-NEXT: [[FCMNE_PPzZ0_D:%[0-9]+]]:ppr = nofpexcept FCMNE_PPzZ0_D [[PTRUE_D]], [[COPY]]
    ; DISABLED-NEXT: [[FCMNE_PPzZ0_D1:%[0-9]+]]:ppr = nofpexcept FCMNE_PPzZ0_D [[PTRUE_S]], [[COPY1]]
    ; DISABLED-NEXT: RET_ReallyLR
    %2:zpr = COPY $z0
    %3:zpr = COPY $z1
    %0:ppr_3b = PTRUE_S 31, implicit $vg
    %1:ppr_3b = PTRUE_D 31, implicit $vg
    %4:ppr = nofpexcept FCMNE_PPzZ0_D %1, %2
    %5:ppr = nofpexcept FCMNE_PPzZ0_D %0, %3
    RET_ReallyLR

...
---
name:            ptrue_d_replaces_ptrue_s_for_d_user_ld1_st1_reg_imm
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr64common }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: ppr_3b }
  - { id: 3, class: zpr }
  - { id: 4, class: zpr }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $x0, $z0

    ; ENABLED-LABEL: name: ptrue_d_replaces_ptrue_s_for_d_user_ld1_st1_reg_imm
    ; ENABLED: liveins: $x0, $z0
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; ENABLED-NEXT: [[LD1W_D_IMM:%[0-9]+]]:zpr = LD1W_D_IMM [[PTRUE_D]], [[COPY]], 0 :: (load (<vscale x 1 x s64>))
    ; ENABLED-NEXT: ST1W_IMM [[COPY1]], [[PTRUE_D]], [[COPY]], 0 :: (store (<vscale x 4 x s32>))
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: ptrue_d_replaces_ptrue_s_for_d_user_ld1_st1_reg_imm
    ; DISABLED: liveins: $x0, $z0
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; DISABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; DISABLED-NEXT: [[LD1W_D_IMM:%[0-9]+]]:zpr = LD1W_D_IMM [[PTRUE_S]], [[COPY]], 0 :: (load (<vscale x 1 x s64>))
    ; DISABLED-NEXT: ST1W_IMM [[COPY1]], [[PTRUE_D]], [[COPY]], 0 :: (store (<vscale x 4 x s32>))
    ; DISABLED-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %3:zpr = COPY $z0
    %1:ppr_3b = PTRUE_S 31, implicit $vg
    %2:ppr_3b = PTRUE_D 31, implicit $vg
    %4:zpr = LD1W_D_IMM %1, %0, 0 :: (load (<vscale x 1 x s64>))
    ST1W_IMM %3, %2, %0, 0 :: (store (<vscale x 4 x s32>))
    RET_ReallyLR

...
---
name:            ptrue_d_replaces_ptrue_s_for_d_user_ld1_st1_reg_reg
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr64common }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: ppr_3b }
  - { id: 3, class: zpr }
  - { id: 4, class: zpr }
  - { id: 5, class: gpr64common }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
  - { reg: '$x1', virtual-reg: '%5' }
  - { reg: '$z0', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $x0, $x1, $z0

    ; ENABLED-LABEL: name: ptrue_d_replaces_ptrue_s_for_d_user_ld1_st1_reg_reg
    ; ENABLED: liveins: $x0, $x1, $z0
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
    ; ENABLED-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; ENABLED-NEXT: [[LD1W_D:%[0-9]+]]:zpr = LD1W_D [[PTRUE_D]], [[COPY]], [[COPY1]] :: (load (<vscale x 1 x s64>))
    ; ENABLED-NEXT: ST1W [[COPY2]], [[PTRUE_D]], [[COPY]], [[COPY1]] :: (store (<vscale x 4 x s32>))
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: ptrue_d_replaces_ptrue_s_for_d_user_ld1_st1_reg_reg
    ; DISABLED: liveins: $x0, $x1, $z0
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
    ; DISABLED-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; DISABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; DISABLED-NEXT: [[LD1W_D:%[0-9]+]]:zpr = LD1W_D [[PTRUE_S]], [[COPY]], [[COPY1]] :: (load (<vscale x 1 x s64>))
    ; DISABLED-NEXT: ST1W [[COPY2]], [[PTRUE_D]], [[COPY]], [[COPY1]] :: (store (<vscale x 4 x s32>))
    ; DISABLED-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %5:gpr64common = COPY $x1
    %3:zpr = COPY $z0
    %1:ppr_3b = PTRUE_S 31, implicit $vg
    %2:ppr_3b = PTRUE_D 31, implicit $vg
    %4:zpr = LD1W_D %1, %0, %5 :: (load (<vscale x 1 x s64>))
    ST1W %3, %2, %0, %5 :: (store (<vscale x 4 x s32>))
    RET_ReallyLR

...
---
name:            ptrue_s_replaces_ptrue_d_for_d_user_ld1r_reg_imm
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr64common }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: ppr_3b }
  - { id: 3, class: zpr }
  - { id: 4, class: zpr }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $x0, $z0

    ; ENABLED-LABEL: name: ptrue_s_replaces_ptrue_d_for_d_user_ld1r_reg_imm
    ; ENABLED: liveins: $x0, $z0
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; ENABLED-NEXT: [[LD1RW_D_IMM:%[0-9]+]]:zpr = LD1RW_D_IMM [[PTRUE_S]], [[COPY]], 0 :: (load (<vscale x 1 x s64>))
    ; ENABLED-NEXT: [[FCMNE_PPzZ0_D:%[0-9]+]]:ppr = nofpexcept FCMNE_PPzZ0_D [[PTRUE_S]], [[COPY1]]
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: ptrue_s_replaces_ptrue_d_for_d_user_ld1r_reg_imm
    ; DISABLED: liveins: $x0, $z0
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; DISABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; DISABLED-NEXT: [[LD1RW_D_IMM:%[0-9]+]]:zpr = LD1RW_D_IMM [[PTRUE_S]], [[COPY]], 0 :: (load (<vscale x 1 x s64>))
    ; DISABLED-NEXT: [[FCMNE_PPzZ0_D:%[0-9]+]]:ppr = nofpexcept FCMNE_PPzZ0_D [[PTRUE_D]], [[COPY1]]
    ; DISABLED-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %3:zpr = COPY $z0
    %1:ppr_3b = PTRUE_S 31, implicit $vg
    %2:ppr_3b = PTRUE_D 31, implicit $vg
    %4:zpr = LD1RW_D_IMM %1, %0, 0 :: (load (<vscale x 1 x s64>))
    %5:ppr = nofpexcept FCMNE_PPzZ0_D %2, %3
    RET_ReallyLR

...
---
name:            ptrue_d_replaces_ptrue_s_for_d_user_ldnt1_stnt1_reg_imm
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr64common }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: ppr_3b }
  - { id: 3, class: zpr }
  - { id: 4, class: zpr }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $x0, $z0

    ; ENABLED-LABEL: name: ptrue_d_replaces_ptrue_s_for_d_user_ldnt1_stnt1_reg_imm
    ; ENABLED: liveins: $x0, $z0
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; ENABLED-NEXT: [[LDNT1D_ZRI:%[0-9]+]]:zpr = LDNT1D_ZRI [[PTRUE_D]], [[COPY]], 0 :: (load (<vscale x 1 x s64>))
    ; ENABLED-NEXT: STNT1W_ZRI [[COPY1]], [[PTRUE_D]], [[COPY]], 0 :: (store (<vscale x 4 x s32>))
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: ptrue_d_replaces_ptrue_s_for_d_user_ldnt1_stnt1_reg_imm
    ; DISABLED: liveins: $x0, $z0
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; DISABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; DISABLED-NEXT: [[LDNT1D_ZRI:%[0-9]+]]:zpr = LDNT1D_ZRI [[PTRUE_S]], [[COPY]], 0 :: (load (<vscale x 1 x s64>))
    ; DISABLED-NEXT: STNT1W_ZRI [[COPY1]], [[PTRUE_D]], [[COPY]], 0 :: (store (<vscale x 4 x s32>))
    ; DISABLED-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %3:zpr = COPY $z0
    %1:ppr_3b = PTRUE_S 31, implicit $vg
    %2:ppr_3b = PTRUE_D 31, implicit $vg
    %4:zpr = LDNT1D_ZRI %1, %0, 0 :: (load (<vscale x 1 x s64>))
    STNT1W_ZRI %3, %2, %0, 0 :: (store (<vscale x 4 x s32>))
    RET_ReallyLR

...
---
name:            ptrue_d_replaces_ptrue_s_for_d_user_ldnt1_stnt1_reg_reg
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr64common }
  - { id: 1, class: ppr_3b }
  - { id: 2, class: ppr_3b }
  - { id: 3, class: zpr }
  - { id: 4, class: zpr }
  - { id: 5, class: gpr64common }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
  - { reg: '$x1', virtual-reg: '%5' }
  - { reg: '$z0', virtual-reg: '%3' }
body:             |
  bb.0:
    liveins: $x0, $x1, $z0

    ; ENABLED-LABEL: name: ptrue_d_replaces_ptrue_s_for_d_user_ldnt1_stnt1_reg_reg
    ; ENABLED: liveins: $x0, $x1, $z0
    ; ENABLED-NEXT: {{  $}}
    ; ENABLED-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; ENABLED-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
    ; ENABLED-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z0
    ; ENABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; ENABLED-NEXT: [[LDNT1D_ZRR:%[0-9]+]]:zpr = LDNT1D_ZRR [[PTRUE_D]], [[COPY]], [[COPY1]] :: (load (<vscale x 1 x s64>))
    ; ENABLED-NEXT: STNT1W_ZRR [[COPY2]], [[PTRUE_D]], [[COPY]], [[COPY1]] :: (store (<vscale x 4 x s32>))
    ; ENABLED-NEXT: RET_ReallyLR
    ;
    ; DISABLED-LABEL: name: ptrue_d_replaces_ptrue_s_for_d_user_ldnt1_stnt1_reg_reg
    ; DISABLED: liveins: $x0, $x1, $z0
    ; DISABLED-NEXT: {{  $}}
    ; DISABLED-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; DISABLED-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
    ; DISABLED-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY $z0
    ; DISABLED-NEXT: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31, implicit $vg
    ; DISABLED-NEXT: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31, implicit $vg
    ; DISABLED-NEXT: [[LDNT1D_ZRR:%[0-9]+]]:zpr = LDNT1D_ZRR [[PTRUE_S]], [[COPY]], [[COPY1]] :: (load (<vscale x 1 x s64>))
    ; DISABLED-NEXT: STNT1W_ZRR [[COPY2]], [[PTRUE_D]], [[COPY]], [[COPY1]] :: (store (<vscale x 4 x s32>))
    ; DISABLED-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %5:gpr64common = COPY $x1
    %3:zpr = COPY $z0
    %1:ppr_3b = PTRUE_S 31, implicit $vg
    %2:ppr_3b = PTRUE_D 31, implicit $vg
    %4:zpr = LDNT1D_ZRR %1, %0, %5 :: (load (<vscale x 1 x s64>))
    STNT1W_ZRR %3, %2, %0, %5 :: (store (<vscale x 4 x s32>))
    RET_ReallyLR

...