llvm/test/CodeGen/AArch64/sve-mask-partition.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s

;; Scalable
define <vscale x 16 x i1> @mask_exclude_active_nxv16(<vscale x 16 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_nxv16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.b
; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1(<vscale x 16 x i1> %mask.in, i1 false)
  %mask.out = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 %tz.elts)
  ret <vscale x 16 x i1> %mask.out
}

define <vscale x 8 x i1> @mask_exclude_active_nxv8(<vscale x 8 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_nxv8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.h
; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1(<vscale x 8 x i1> %mask.in, i1 false)
  %mask.out = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64 0, i64 %tz.elts)
  ret <vscale x 8 x i1> %mask.out
}

define <vscale x 4 x i1> @mask_exclude_active_nxv4(<vscale x 4 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_nxv4:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.s
; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1(<vscale x 4 x i1> %mask.in, i1 false)
  %mask.out = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 %tz.elts)
  ret <vscale x 4 x i1> %mask.out
}

define <vscale x 2 x i1> @mask_exclude_active_nxv2(<vscale x 2 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_nxv2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.d
; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1(<vscale x 2 x i1> %mask.in, i1 false)
  %mask.out = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 %tz.elts)
  ret <vscale x 2 x i1> %mask.out
}

define <vscale x 16 x i1> @mask_include_active_nxv16(<vscale x 16 x i1> %mask.in) {
; CHECK-LABEL: mask_include_active_nxv16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.b
; CHECK-NEXT:    brka p0.b, p1/z, p0.b
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1(<vscale x 16 x i1> %mask.in, i1 false)
  %inc = add i64 %tz.elts, 1
  %mask.out = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 %inc)
  ret <vscale x 16 x i1> %mask.out
}

define <vscale x 8 x i1> @mask_include_active_nxv8(<vscale x 8 x i1> %mask.in) {
; CHECK-LABEL: mask_include_active_nxv8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.h
; CHECK-NEXT:    brka p0.b, p1/z, p0.b
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1(<vscale x 8 x i1> %mask.in, i1 false)
  %inc = add i64 %tz.elts, 1
  %mask.out = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64 0, i64 %inc)
  ret <vscale x 8 x i1> %mask.out
}

define <vscale x 4 x i1> @mask_include_active_nxv4(<vscale x 4 x i1> %mask.in) {
; CHECK-LABEL: mask_include_active_nxv4:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.s
; CHECK-NEXT:    brka p0.b, p1/z, p0.b
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1(<vscale x 4 x i1> %mask.in, i1 false)
  %inc = add i64 %tz.elts, 1
  %mask.out = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 %inc)
  ret <vscale x 4 x i1> %mask.out
}

define <vscale x 2 x i1> @mask_include_active_nxv2(<vscale x 2 x i1> %mask.in) {
; CHECK-LABEL: mask_include_active_nxv2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.d
; CHECK-NEXT:    brka p0.b, p1/z, p0.b
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1(<vscale x 2 x i1> %mask.in, i1 false)
  %inc = add i64 %tz.elts, 1
  %mask.out = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 %inc)
  ret <vscale x 2 x i1> %mask.out
}

;; Fixed
define <16 x i1> @mask_exclude_active_v16(<16 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_v16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.16b, v0.16b, #7
; CHECK-NEXT:    ptrue p0.b, vl16
; CHECK-NEXT:    cmpne p1.b, p0/z, z0.b, #0
; CHECK-NEXT:    brkb p1.b, p0/z, p1.b
; CHECK-NEXT:    mov z0.b, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v16i1(<16 x i1> %mask.in, i1 false)
  %mask.out = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 0, i64 %tz.elts)
  ret <16 x i1> %mask.out
}

define <8 x i1> @mask_exclude_active_v8(<8 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_v8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.8b, v0.8b, #7
; CHECK-NEXT:    ptrue p0.b, vl8
; CHECK-NEXT:    cmpne p1.b, p0/z, z0.b, #0
; CHECK-NEXT:    brkb p1.b, p0/z, p1.b
; CHECK-NEXT:    mov z0.b, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> %mask.in, i1 false)
  %mask.out = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 0, i64 %tz.elts)
  ret <8 x i1> %mask.out
}

define <4 x i1> @mask_exclude_active_v4(<4 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_v4:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.4h, v0.4h, #15
; CHECK-NEXT:    ptrue p0.h, vl4
; CHECK-NEXT:    cmpne p1.h, p0/z, z0.h, #0
; CHECK-NEXT:    brkb p1.b, p0/z, p1.b
; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> %mask.in, i1 false)
  %mask.out = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 0, i64 %tz.elts)
  ret <4 x i1> %mask.out
}

define <2 x i1> @mask_exclude_active_v2(<2 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_v2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.2s, v0.2s, #31
; CHECK-NEXT:    ptrue p0.s, vl2
; CHECK-NEXT:    cmpne p1.s, p0/z, z0.s, #0
; CHECK-NEXT:    brkb p1.b, p0/z, p1.b
; CHECK-NEXT:    mov z0.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v2i1(<2 x i1> %mask.in, i1 false)
  %mask.out = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 0, i64 %tz.elts)
  ret <2 x i1> %mask.out
}

define <16 x i1> @mask_include_active_v16(<16 x i1> %mask.in) {
; CHECK-LABEL: mask_include_active_v16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.16b, v0.16b, #7
; CHECK-NEXT:    ptrue p0.b, vl16
; CHECK-NEXT:    cmpne p1.b, p0/z, z0.b, #0
; CHECK-NEXT:    brka p1.b, p0/z, p1.b
; CHECK-NEXT:    mov z0.b, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v16i1(<16 x i1> %mask.in, i1 false)
  %inc = add i64 %tz.elts, 1
  %mask.out = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 0, i64 %inc)
  ret <16 x i1> %mask.out
}

define <8 x i1> @mask_include_active_v8(<8 x i1> %mask.in) {
; CHECK-LABEL: mask_include_active_v8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.8b, v0.8b, #7
; CHECK-NEXT:    ptrue p0.b, vl8
; CHECK-NEXT:    cmpne p1.b, p0/z, z0.b, #0
; CHECK-NEXT:    brka p1.b, p0/z, p1.b
; CHECK-NEXT:    mov z0.b, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> %mask.in, i1 false)
  %inc = add i64 %tz.elts, 1
  %mask.out = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 0, i64 %inc)
  ret <8 x i1> %mask.out
}

define <4 x i1> @mask_include_active_v4(<4 x i1> %mask.in) {
; CHECK-LABEL: mask_include_active_v4:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.4h, v0.4h, #15
; CHECK-NEXT:    ptrue p0.h, vl4
; CHECK-NEXT:    cmpne p1.h, p0/z, z0.h, #0
; CHECK-NEXT:    brka p1.b, p0/z, p1.b
; CHECK-NEXT:    mov z0.h, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> %mask.in, i1 false)
  %inc = add i64 %tz.elts, 1
  %mask.out = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 0, i64 %inc)
  ret <4 x i1> %mask.out
}

define <2 x i1> @mask_include_active_v2(<2 x i1> %mask.in) {
; CHECK-LABEL: mask_include_active_v2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.2s, v0.2s, #31
; CHECK-NEXT:    ptrue p0.s, vl2
; CHECK-NEXT:    cmpne p1.s, p0/z, z0.s, #0
; CHECK-NEXT:    brka p1.b, p0/z, p1.b
; CHECK-NEXT:    mov z0.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v2i1(<2 x i1> %mask.in, i1 false)
  %inc = add i64 %tz.elts, 1
  %mask.out = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 0, i64 %inc)
  ret <2 x i1> %mask.out
}

;; Wider-than-legal tests
define <vscale x 32 x i1> @mask_exclude_active_nxv32(<vscale x 32 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_nxv32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p2.b
; CHECK-NEXT:    rdvl x8, #1
; CHECK-NEXT:    mov x9, x8
; CHECK-NEXT:    brkb p0.b, p2/z, p0.b
; CHECK-NEXT:    brkb p1.b, p2/z, p1.b
; CHECK-NEXT:    cntp x10, p0, p0.b
; CHECK-NEXT:    incp x9, p1.b
; CHECK-NEXT:    cmp x10, x8
; CHECK-NEXT:    csel x9, x10, x9, ne
; CHECK-NEXT:    whilelo p0.b, xzr, x9
; CHECK-NEXT:    whilelo p1.b, x8, x9
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1(<vscale x 32 x i1> %mask.in, i1 false)
  %mask.out = call <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i64(i64 0, i64 %tz.elts)
  ret <vscale x 32 x i1> %mask.out
}

define <32 x i1> @mask_exclude_active_v32(<32 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_v32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr w9, [sp, #64]
; CHECK-NEXT:    fmov s0, w0
; CHECK-NEXT:    ldr w10, [sp, #72]
; CHECK-NEXT:    ptrue p0.b, vl16
; CHECK-NEXT:    mov w11, #16 // =0x10
; CHECK-NEXT:    fmov s1, w9
; CHECK-NEXT:    ldr w9, [sp, #80]
; CHECK-NEXT:    mov v0.b[1], w1
; CHECK-NEXT:    mov v1.b[1], w10
; CHECK-NEXT:    ldr w10, [sp, #128]
; CHECK-NEXT:    mov v0.b[2], w2
; CHECK-NEXT:    mov v1.b[2], w9
; CHECK-NEXT:    ldr w9, [sp, #88]
; CHECK-NEXT:    mov v0.b[3], w3
; CHECK-NEXT:    mov v1.b[3], w9
; CHECK-NEXT:    ldr w9, [sp, #96]
; CHECK-NEXT:    mov v0.b[4], w4
; CHECK-NEXT:    mov v1.b[4], w9
; CHECK-NEXT:    ldr w9, [sp, #104]
; CHECK-NEXT:    mov v0.b[5], w5
; CHECK-NEXT:    mov v1.b[5], w9
; CHECK-NEXT:    ldr w9, [sp, #112]
; CHECK-NEXT:    mov v0.b[6], w6
; CHECK-NEXT:    mov v1.b[6], w9
; CHECK-NEXT:    ldr w9, [sp, #120]
; CHECK-NEXT:    mov v0.b[7], w7
; CHECK-NEXT:    mov v1.b[7], w9
; CHECK-NEXT:    ldr w9, [sp]
; CHECK-NEXT:    mov v0.b[8], w9
; CHECK-NEXT:    ldr w9, [sp, #8]
; CHECK-NEXT:    mov v1.b[8], w10
; CHECK-NEXT:    ldr w10, [sp, #136]
; CHECK-NEXT:    mov v0.b[9], w9
; CHECK-NEXT:    ldr w9, [sp, #16]
; CHECK-NEXT:    mov v1.b[9], w10
; CHECK-NEXT:    ldr w10, [sp, #144]
; CHECK-NEXT:    mov v0.b[10], w9
; CHECK-NEXT:    ldr w9, [sp, #24]
; CHECK-NEXT:    mov v1.b[10], w10
; CHECK-NEXT:    ldr w10, [sp, #152]
; CHECK-NEXT:    mov v0.b[11], w9
; CHECK-NEXT:    ldr w9, [sp, #32]
; CHECK-NEXT:    mov v1.b[11], w10
; CHECK-NEXT:    ldr w10, [sp, #160]
; CHECK-NEXT:    mov v0.b[12], w9
; CHECK-NEXT:    ldr w9, [sp, #40]
; CHECK-NEXT:    mov v1.b[12], w10
; CHECK-NEXT:    ldr w10, [sp, #168]
; CHECK-NEXT:    mov v0.b[13], w9
; CHECK-NEXT:    ldr w9, [sp, #48]
; CHECK-NEXT:    mov v1.b[13], w10
; CHECK-NEXT:    ldr w10, [sp, #176]
; CHECK-NEXT:    mov v0.b[14], w9
; CHECK-NEXT:    ldr w9, [sp, #56]
; CHECK-NEXT:    mov v1.b[14], w10
; CHECK-NEXT:    ldr w10, [sp, #184]
; CHECK-NEXT:    mov v0.b[15], w9
; CHECK-NEXT:    mov v1.b[15], w10
; CHECK-NEXT:    shl v0.16b, v0.16b, #7
; CHECK-NEXT:    shl v1.16b, v1.16b, #7
; CHECK-NEXT:    cmpne p1.b, p0/z, z0.b, #0
; CHECK-NEXT:    cmpne p2.b, p0/z, z1.b, #0
; CHECK-NEXT:    brkb p1.b, p0/z, p1.b
; CHECK-NEXT:    brkb p2.b, p0/z, p2.b
; CHECK-NEXT:    cntp x9, p1, p1.b
; CHECK-NEXT:    cntp x10, p2, p2.b
; CHECK-NEXT:    cmp x9, #16
; CHECK-NEXT:    add x10, x10, #16
; CHECK-NEXT:    csel x9, x9, x10, ne
; CHECK-NEXT:    whilelo p0.b, x11, x9
; CHECK-NEXT:    whilelo p1.b, xzr, x9
; CHECK-NEXT:    adrp x9, .LCPI17_0
; CHECK-NEXT:    mov z0.b, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI17_0]
; CHECK-NEXT:    mov z2.b, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    and v1.16b, v2.16b, v1.16b
; CHECK-NEXT:    addp v0.16b, v0.16b, v0.16b
; CHECK-NEXT:    addp v1.16b, v1.16b, v1.16b
; CHECK-NEXT:    addp v0.16b, v0.16b, v0.16b
; CHECK-NEXT:    addp v1.16b, v1.16b, v1.16b
; CHECK-NEXT:    addp v0.16b, v0.16b, v0.16b
; CHECK-NEXT:    addp v1.16b, v1.16b, v1.16b
; CHECK-NEXT:    str h0, [x8, #2]
; CHECK-NEXT:    str h1, [x8]
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v32i1(<32 x i1> %mask.in, i1 false)
  %mask.out = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 0, i64 %tz.elts)
  ret <32 x i1> %mask.out
}

;; Non-matches
define <vscale x 16 x i1> @mask_exclude_active_nxv16_nonzero_lower_bound(<vscale x 16 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_nxv16_nonzero_lower_bound:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.b
; CHECK-NEXT:    mov w9, #1 // =0x1
; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
; CHECK-NEXT:    cntp x8, p0, p0.b
; CHECK-NEXT:    whilelo p0.b, x9, x8
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1(<vscale x 16 x i1> %mask.in, i1 false)
  %mask.out = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 1, i64 %tz.elts)
  ret <vscale x 16 x i1> %mask.out
}

define <vscale x 4 x i1> @mask_exclude_active_narrower_result_type(<vscale x 8 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_narrower_result_type:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.h
; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
; CHECK-NEXT:    cntp x8, p0, p0.h
; CHECK-NEXT:    whilelo p0.s, xzr, x8
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts(<vscale x 8 x i1> %mask.in, i1 false)
  %mask.out = call <vscale x 4 x i1> @llvm.get.active.lane.mask(i64 0, i64 %tz.elts)
  ret <vscale x 4 x i1> %mask.out
}

define <vscale x 16 x i1> @mask_exclude_active_wider_result_type(<vscale x 8 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_wider_result_type:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p1.h
; CHECK-NEXT:    brkb p0.b, p1/z, p0.b
; CHECK-NEXT:    cntp x8, p0, p0.h
; CHECK-NEXT:    whilelo p0.b, xzr, x8
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts(<vscale x 8 x i1> %mask.in, i1 false)
  %mask.out = call <vscale x 16 x i1> @llvm.get.active.lane.mask(i64 0, i64 %tz.elts)
  ret <vscale x 16 x i1> %mask.out
}

define <4 x i1> @mask_exclude_active_narrower_result_type_fixed(<8 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_narrower_result_type_fixed:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.8b, v0.8b, #7
; CHECK-NEXT:    ptrue p0.b, vl8
; CHECK-NEXT:    cmpne p1.b, p0/z, z0.b, #0
; CHECK-NEXT:    brkb p1.b, p0/z, p1.b
; CHECK-NEXT:    cntp x8, p1, p1.b
; CHECK-NEXT:    whilelo p0.h, xzr, x8
; CHECK-NEXT:    mov z0.h, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts(<8 x i1> %mask.in, i1 false)
  %mask.out = call <4 x i1> @llvm.get.active.lane.mask(i64 0, i64 %tz.elts)
  ret <4 x i1> %mask.out
}

define <16 x i1> @mask_exclude_active_wider_result_type_fixed(<8 x i1> %mask.in) {
; CHECK-LABEL: mask_exclude_active_wider_result_type_fixed:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.8b, v0.8b, #7
; CHECK-NEXT:    ptrue p0.b, vl8
; CHECK-NEXT:    cmpne p1.b, p0/z, z0.b, #0
; CHECK-NEXT:    brkb p1.b, p0/z, p1.b
; CHECK-NEXT:    mov z0.b, p1/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    ret
  %tz.elts = call i64 @llvm.experimental.cttz.elts(<8 x i1> %mask.in, i1 false)
  %mask.out = call <16 x i1> @llvm.get.active.lane.mask(i64 0, i64 %tz.elts)
  ret <16 x i1> %mask.out
}