llvm/test/CodeGen/AArch64/smulh.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI

define i16 @smulh_i16(i16 %x, i16 %y) nounwind {
; CHECK-SD-LABEL: smulh_i16:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    sxth w8, w1
; CHECK-SD-NEXT:    sxth w9, w0
; CHECK-SD-NEXT:    mul w8, w9, w8
; CHECK-SD-NEXT:    lsr w0, w8, #16
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: smulh_i16:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    sxth w8, w0
; CHECK-GI-NEXT:    sxth w9, w1
; CHECK-GI-NEXT:    mul w8, w8, w9
; CHECK-GI-NEXT:    asr w0, w8, #16
; CHECK-GI-NEXT:    ret
  %r = call i16 @llvm.smulh(i16 %x, i16 %y)
  ret i16 %r
}

define i32 @smulh_i32(i32 %x, i32 %y) nounwind {
; CHECK-SD-LABEL: smulh_i32:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    smull x8, w0, w1
; CHECK-SD-NEXT:    lsr x0, x8, #32
; CHECK-SD-NEXT:    // kill: def $w0 killed $w0 killed $x0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: smulh_i32:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    smull x8, w0, w1
; CHECK-GI-NEXT:    asr x0, x8, #32
; CHECK-GI-NEXT:    // kill: def $w0 killed $w0 killed $x0
; CHECK-GI-NEXT:    ret
  %r = call i32 @llvm.smulh(i32 %x, i32 %y)
  ret i32 %r
}

define i64 @smulh_i64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: smulh_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smulh x0, x0, x1
; CHECK-NEXT:    ret
  %r = call i64 @llvm.smulh(i64 %x, i64 %y)
  ret i64 %r
}

define i96 @smulh_i96(i96 %x, i96 %y) nounwind {
; CHECK-SD-LABEL: smulh_i96:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    extr x9, x1, x0, #32
; CHECK-SD-NEXT:    lsl x10, x0, #32
; CHECK-SD-NEXT:    sxtw x13, w3
; CHECK-SD-NEXT:    sbfx x8, x1, #31, #1
; CHECK-SD-NEXT:    umulh x12, x10, x2
; CHECK-SD-NEXT:    asr x16, x13, #63
; CHECK-SD-NEXT:    mul x14, x9, x2
; CHECK-SD-NEXT:    mul x8, x8, x2
; CHECK-SD-NEXT:    umulh x11, x9, x2
; CHECK-SD-NEXT:    adds x12, x14, x12
; CHECK-SD-NEXT:    mul x17, x10, x13
; CHECK-SD-NEXT:    umulh x15, x10, x13
; CHECK-SD-NEXT:    adc x8, x11, x8
; CHECK-SD-NEXT:    mul x10, x10, x16
; CHECK-SD-NEXT:    asr x11, x8, #63
; CHECK-SD-NEXT:    cmn x17, x12
; CHECK-SD-NEXT:    mul x16, x9, x13
; CHECK-SD-NEXT:    smulh x9, x9, x13
; CHECK-SD-NEXT:    adc x10, x15, x10
; CHECK-SD-NEXT:    asr x12, x10, #63
; CHECK-SD-NEXT:    adds x8, x8, x10
; CHECK-SD-NEXT:    adc x10, x11, x12
; CHECK-SD-NEXT:    adds x0, x16, x8
; CHECK-SD-NEXT:    adc x1, x9, x10
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: smulh_i96:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    sxtw x8, w1
; CHECK-GI-NEXT:    sxtw x10, w3
; CHECK-GI-NEXT:    umulh x9, x0, x2
; CHECK-GI-NEXT:    umulh x11, x8, x2
; CHECK-GI-NEXT:    asr x14, x10, #63
; CHECK-GI-NEXT:    umulh x12, x0, x10
; CHECK-GI-NEXT:    mul x13, x0, x10
; CHECK-GI-NEXT:    mul x15, x8, x2
; CHECK-GI-NEXT:    add x11, x11, x12
; CHECK-GI-NEXT:    asr x12, x8, #63
; CHECK-GI-NEXT:    madd x11, x0, x14, x11
; CHECK-GI-NEXT:    adds x9, x9, x13
; CHECK-GI-NEXT:    smaddl x8, w8, w10, x11
; CHECK-GI-NEXT:    cset w10, hs
; CHECK-GI-NEXT:    adds x9, x9, x15
; CHECK-GI-NEXT:    madd x8, x12, x2, x8
; CHECK-GI-NEXT:    cset w11, hs
; CHECK-GI-NEXT:    and x10, x10, #0x1
; CHECK-GI-NEXT:    and x11, x11, #0x1
; CHECK-GI-NEXT:    add x10, x10, x11
; CHECK-GI-NEXT:    add x8, x8, x10
; CHECK-GI-NEXT:    asr x10, x8, #63
; CHECK-GI-NEXT:    extr x0, x8, x9, #32
; CHECK-GI-NEXT:    extr x1, x10, x8, #32
; CHECK-GI-NEXT:    ret
  %r = call i96 @llvm.smulh(i96 %x, i96 %y)
  ret i96 %r
}

define i128 @smulh_i128(i128 %x, i128 %y) nounwind {
; CHECK-SD-LABEL: smulh_i128:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    asr x9, x1, #63
; CHECK-SD-NEXT:    umulh x10, x0, x2
; CHECK-SD-NEXT:    asr x13, x3, #63
; CHECK-SD-NEXT:    mul x11, x1, x2
; CHECK-SD-NEXT:    umulh x8, x1, x2
; CHECK-SD-NEXT:    mul x9, x9, x2
; CHECK-SD-NEXT:    adds x10, x11, x10
; CHECK-SD-NEXT:    mul x14, x0, x3
; CHECK-SD-NEXT:    umulh x12, x0, x3
; CHECK-SD-NEXT:    adc x8, x8, x9
; CHECK-SD-NEXT:    mul x13, x0, x13
; CHECK-SD-NEXT:    asr x11, x8, #63
; CHECK-SD-NEXT:    cmn x14, x10
; CHECK-SD-NEXT:    mul x15, x1, x3
; CHECK-SD-NEXT:    smulh x9, x1, x3
; CHECK-SD-NEXT:    adc x10, x12, x13
; CHECK-SD-NEXT:    asr x12, x10, #63
; CHECK-SD-NEXT:    adds x8, x8, x10
; CHECK-SD-NEXT:    adc x10, x11, x12
; CHECK-SD-NEXT:    adds x0, x15, x8
; CHECK-SD-NEXT:    adc x1, x9, x10
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: smulh_i128:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    asr x8, x1, #63
; CHECK-GI-NEXT:    asr x14, x3, #63
; CHECK-GI-NEXT:    umulh x15, x1, x3
; CHECK-GI-NEXT:    umulh x13, x8, x2
; CHECK-GI-NEXT:    umulh x16, x0, x14
; CHECK-GI-NEXT:    umulh x9, x0, x2
; CHECK-GI-NEXT:    add x13, x13, x15
; CHECK-GI-NEXT:    mul x10, x0, x3
; CHECK-GI-NEXT:    add x13, x13, x16
; CHECK-GI-NEXT:    mul x11, x1, x2
; CHECK-GI-NEXT:    umulh x12, x1, x2
; CHECK-GI-NEXT:    adds x9, x9, x10
; CHECK-GI-NEXT:    umulh x17, x0, x3
; CHECK-GI-NEXT:    madd x13, x0, x14, x13
; CHECK-GI-NEXT:    mul x18, x0, x14
; CHECK-GI-NEXT:    mul x15, x1, x3
; CHECK-GI-NEXT:    madd x10, x1, x14, x13
; CHECK-GI-NEXT:    cset w13, hs
; CHECK-GI-NEXT:    cmn x9, x11
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    adds x11, x12, x17
; CHECK-GI-NEXT:    and x13, x13, #0x1
; CHECK-GI-NEXT:    mul x12, x8, x2
; CHECK-GI-NEXT:    cset w14, hs
; CHECK-GI-NEXT:    adds x11, x11, x18
; CHECK-GI-NEXT:    cset w16, hs
; CHECK-GI-NEXT:    and x9, x9, #0x1
; CHECK-GI-NEXT:    and x14, x14, #0x1
; CHECK-GI-NEXT:    madd x10, x8, x3, x10
; CHECK-GI-NEXT:    and x16, x16, #0x1
; CHECK-GI-NEXT:    adds x11, x11, x15
; CHECK-GI-NEXT:    add x9, x13, x9
; CHECK-GI-NEXT:    add x13, x14, x16
; CHECK-GI-NEXT:    cset w14, hs
; CHECK-GI-NEXT:    adds x11, x11, x12
; CHECK-GI-NEXT:    madd x8, x8, x2, x10
; CHECK-GI-NEXT:    and x10, x14, #0x1
; CHECK-GI-NEXT:    cset w12, hs
; CHECK-GI-NEXT:    adds x0, x11, x9
; CHECK-GI-NEXT:    add x9, x13, x10
; CHECK-GI-NEXT:    and x10, x12, #0x1
; CHECK-GI-NEXT:    cset w11, hs
; CHECK-GI-NEXT:    add x9, x9, x10
; CHECK-GI-NEXT:    and x10, x11, #0x1
; CHECK-GI-NEXT:    add x9, x9, x10
; CHECK-GI-NEXT:    add x1, x8, x9
; CHECK-GI-NEXT:    ret
  %r = call i128 @llvm.smulh(i128 %x, i128 %y)
  ret i128 %r
}

define <8 x i8> @smulh_v8i8(<8 x i8> %x, <8 x i8> %y) nounwind {
; CHECK-LABEL: smulh_v8i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smull v0.8h, v0.8b, v1.8b
; CHECK-NEXT:    shrn v0.8b, v0.8h, #8
; CHECK-NEXT:    ret
  %r = call <8 x i8> @llvm.smulh(<8 x i8> %x, <8 x i8> %y)
  ret <8 x i8> %r
}

define <4 x i16> @smulh_v4i16(<4 x i16> %x, <4 x i16> %y) nounwind {
; CHECK-LABEL: smulh_v4i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smull v0.4s, v0.4h, v1.4h
; CHECK-NEXT:    shrn v0.4h, v0.4s, #16
; CHECK-NEXT:    ret
  %r = call <4 x i16> @llvm.smulh(<4 x i16> %x, <4 x i16> %y)
  ret <4 x i16> %r
}

define <2 x i32> @smulh_v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; CHECK-LABEL: smulh_v2i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smull v0.2d, v0.2s, v1.2s
; CHECK-NEXT:    shrn v0.2s, v0.2d, #32
; CHECK-NEXT:    ret
  %r = call <2 x i32> @llvm.smulh(<2 x i32> %x, <2 x i32> %y)
  ret <2 x i32> %r
}

define <1 x i64> @smulh_v1i64(<1 x i64> %x, <1 x i64> %y) nounwind {
; CHECK-SD-LABEL: smulh_v1i64:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    // kill: def $d1 killed $d1 def $q1
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    fmov x8, d1
; CHECK-SD-NEXT:    fmov x9, d0
; CHECK-SD-NEXT:    smulh x8, x9, x8
; CHECK-SD-NEXT:    fmov d0, x8
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: smulh_v1i64:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    fmov x8, d0
; CHECK-GI-NEXT:    fmov x9, d1
; CHECK-GI-NEXT:    smulh x8, x8, x9
; CHECK-GI-NEXT:    fmov d0, x8
; CHECK-GI-NEXT:    ret
  %r = call <1 x i64> @llvm.smulh(<1 x i64> %x, <1 x i64> %y)
  ret <1 x i64> %r
}

define <16 x i8> @smulh_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: smulh_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smull2 v2.8h, v0.16b, v1.16b
; CHECK-NEXT:    smull v0.8h, v0.8b, v1.8b
; CHECK-NEXT:    uzp2 v0.16b, v0.16b, v2.16b
; CHECK-NEXT:    ret
  %r = call <16 x i8> @llvm.smulh(<16 x i8> %x, <16 x i8> %y)
  ret <16 x i8> %r
}

define <8 x i16> @smulh_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; CHECK-LABEL: smulh_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smull2 v2.4s, v0.8h, v1.8h
; CHECK-NEXT:    smull v0.4s, v0.4h, v1.4h
; CHECK-NEXT:    uzp2 v0.8h, v0.8h, v2.8h
; CHECK-NEXT:    ret
  %r = call <8 x i16> @llvm.smulh(<8 x i16> %x, <8 x i16> %y)
  ret <8 x i16> %r
}

define <4 x i32> @smulh_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: smulh_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    smull2 v2.2d, v0.4s, v1.4s
; CHECK-NEXT:    smull v0.2d, v0.2s, v1.2s
; CHECK-NEXT:    uzp2 v0.4s, v0.4s, v2.4s
; CHECK-NEXT:    ret
  %r = call <4 x i32> @llvm.smulh(<4 x i32> %x, <4 x i32> %y)
  ret <4 x i32> %r
}

define <2 x i64> @smulh_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-SD-LABEL: smulh_v2i64:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    fmov x10, d1
; CHECK-SD-NEXT:    fmov x11, d0
; CHECK-SD-NEXT:    mov x8, v1.d[1]
; CHECK-SD-NEXT:    mov x9, v0.d[1]
; CHECK-SD-NEXT:    smulh x10, x11, x10
; CHECK-SD-NEXT:    smulh x8, x9, x8
; CHECK-SD-NEXT:    fmov d0, x10
; CHECK-SD-NEXT:    mov v0.d[1], x8
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: smulh_v2i64:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    mov d2, v0.d[1]
; CHECK-GI-NEXT:    mov d3, v1.d[1]
; CHECK-GI-NEXT:    fmov x8, d0
; CHECK-GI-NEXT:    fmov x9, d1
; CHECK-GI-NEXT:    umulh x10, x8, x9
; CHECK-GI-NEXT:    fmov x11, d2
; CHECK-GI-NEXT:    fmov x12, d3
; CHECK-GI-NEXT:    asr x13, x9, #63
; CHECK-GI-NEXT:    umulh x14, x11, x12
; CHECK-GI-NEXT:    madd x10, x8, x13, x10
; CHECK-GI-NEXT:    asr x13, x12, #63
; CHECK-GI-NEXT:    asr x8, x8, #63
; CHECK-GI-NEXT:    madd x13, x11, x13, x14
; CHECK-GI-NEXT:    asr x11, x11, #63
; CHECK-GI-NEXT:    madd x8, x8, x9, x10
; CHECK-GI-NEXT:    madd x9, x11, x12, x13
; CHECK-GI-NEXT:    fmov d0, x8
; CHECK-GI-NEXT:    mov v0.d[1], x9
; CHECK-GI-NEXT:    ret
  %r = call <2 x i64> @llvm.smulh(<2 x i64> %x, <2 x i64> %y)
  ret <2 x i64> %r
}

define <3 x i32> @smulh_v3i32(<3 x i32> %x, <3 x i32> %y) nounwind {
; CHECK-SD-LABEL: smulh_v3i32:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    smull2 v2.2d, v0.4s, v1.4s
; CHECK-SD-NEXT:    smull v0.2d, v0.2s, v1.2s
; CHECK-SD-NEXT:    uzp2 v0.4s, v0.4s, v2.4s
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: smulh_v3i32:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    mov v2.s[0], v0.s[0]
; CHECK-GI-NEXT:    mov v3.s[0], v1.s[0]
; CHECK-GI-NEXT:    mov w8, v0.s[2]
; CHECK-GI-NEXT:    mov w9, v1.s[2]
; CHECK-GI-NEXT:    mov v2.s[1], v0.s[1]
; CHECK-GI-NEXT:    mov v3.s[1], v1.s[1]
; CHECK-GI-NEXT:    smull x8, w8, w9
; CHECK-GI-NEXT:    smull v2.2d, v2.2s, v3.2s
; CHECK-GI-NEXT:    asr x8, x8, #32
; CHECK-GI-NEXT:    sshr v2.2d, v2.2d, #32
; CHECK-GI-NEXT:    mov d0, v2.d[1]
; CHECK-GI-NEXT:    fmov x10, d2
; CHECK-GI-NEXT:    fmov x9, d0
; CHECK-GI-NEXT:    fmov s0, w10
; CHECK-GI-NEXT:    mov v0.s[1], w9
; CHECK-GI-NEXT:    mov v0.s[2], w8
; CHECK-GI-NEXT:    ret
  %r = call <3 x i32> @llvm.smulh(<3 x i32> %x, <3 x i32> %y)
  ret <3 x i32> %r
}

define <2 x i48> @smulh_v2i48(<2 x i48> %x, <2 x i48> %y) nounwind {
; CHECK-SD-LABEL: smulh_v2i48:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    shl v1.2d, v1.2d, #16
; CHECK-SD-NEXT:    shl v0.2d, v0.2d, #16
; CHECK-SD-NEXT:    sshr v1.2d, v1.2d, #16
; CHECK-SD-NEXT:    fmov x10, d0
; CHECK-SD-NEXT:    mov x8, v0.d[1]
; CHECK-SD-NEXT:    fmov x11, d1
; CHECK-SD-NEXT:    mov x9, v1.d[1]
; CHECK-SD-NEXT:    smulh x10, x10, x11
; CHECK-SD-NEXT:    smulh x8, x8, x9
; CHECK-SD-NEXT:    fmov d0, x10
; CHECK-SD-NEXT:    mov v0.d[1], x8
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: smulh_v2i48:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    mov d2, v0.d[1]
; CHECK-GI-NEXT:    fmov x8, d0
; CHECK-GI-NEXT:    mov d0, v1.d[1]
; CHECK-GI-NEXT:    fmov x9, d1
; CHECK-GI-NEXT:    lsl x10, x8, #48
; CHECK-GI-NEXT:    sbfx x8, x8, #16, #32
; CHECK-GI-NEXT:    lsl x11, x9, #48
; CHECK-GI-NEXT:    sbfx x9, x9, #16, #32
; CHECK-GI-NEXT:    fmov x12, d2
; CHECK-GI-NEXT:    fmov x13, d0
; CHECK-GI-NEXT:    extr x10, x8, x10, #48
; CHECK-GI-NEXT:    asr x8, x8, #48
; CHECK-GI-NEXT:    extr x11, x9, x11, #48
; CHECK-GI-NEXT:    asr x9, x9, #48
; CHECK-GI-NEXT:    lsl x14, x12, #48
; CHECK-GI-NEXT:    sbfx x12, x12, #16, #32
; CHECK-GI-NEXT:    lsl x16, x13, #48
; CHECK-GI-NEXT:    sbfx x13, x13, #16, #32
; CHECK-GI-NEXT:    umulh x15, x10, x11
; CHECK-GI-NEXT:    extr x14, x12, x14, #48
; CHECK-GI-NEXT:    asr x12, x12, #48
; CHECK-GI-NEXT:    extr x16, x13, x16, #48
; CHECK-GI-NEXT:    asr x13, x13, #48
; CHECK-GI-NEXT:    madd x9, x10, x9, x15
; CHECK-GI-NEXT:    umulh x15, x14, x16
; CHECK-GI-NEXT:    madd x8, x8, x11, x9
; CHECK-GI-NEXT:    madd x13, x14, x13, x15
; CHECK-GI-NEXT:    mul x10, x10, x11
; CHECK-GI-NEXT:    sxtw x8, w8
; CHECK-GI-NEXT:    madd x9, x12, x16, x13
; CHECK-GI-NEXT:    mul x11, x14, x16
; CHECK-GI-NEXT:    extr x8, x8, x10, #48
; CHECK-GI-NEXT:    sxtw x9, w9
; CHECK-GI-NEXT:    fmov d0, x8
; CHECK-GI-NEXT:    extr x9, x9, x11, #48
; CHECK-GI-NEXT:    mov v0.d[1], x9
; CHECK-GI-NEXT:    ret
  %r = call <2 x i48> @llvm.smulh(<2 x i48> %x, <2 x i48> %y)
  ret <2 x i48> %r
}

define <2 x i128> @smulh_v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-SD-LABEL: smulh_v2i128:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    asr x10, x1, #63
; CHECK-SD-NEXT:    asr x8, x5, #63
; CHECK-SD-NEXT:    umulh x11, x0, x4
; CHECK-SD-NEXT:    asr x18, x3, #63
; CHECK-SD-NEXT:    mul x12, x1, x4
; CHECK-SD-NEXT:    umulh x9, x1, x4
; CHECK-SD-NEXT:    mul x10, x10, x4
; CHECK-SD-NEXT:    adds x11, x12, x11
; CHECK-SD-NEXT:    mul x14, x0, x5
; CHECK-SD-NEXT:    umulh x13, x0, x5
; CHECK-SD-NEXT:    adc x9, x9, x10
; CHECK-SD-NEXT:    mul x8, x0, x8
; CHECK-SD-NEXT:    asr x0, x7, #63
; CHECK-SD-NEXT:    cmn x14, x11
; CHECK-SD-NEXT:    asr x11, x9, #63
; CHECK-SD-NEXT:    mul x16, x1, x5
; CHECK-SD-NEXT:    smulh x15, x1, x5
; CHECK-SD-NEXT:    adc x8, x13, x8
; CHECK-SD-NEXT:    umulh x4, x2, x6
; CHECK-SD-NEXT:    asr x12, x8, #63
; CHECK-SD-NEXT:    adds x8, x9, x8
; CHECK-SD-NEXT:    mul x5, x3, x6
; CHECK-SD-NEXT:    adc x9, x11, x12
; CHECK-SD-NEXT:    umulh x17, x3, x6
; CHECK-SD-NEXT:    mul x18, x18, x6
; CHECK-SD-NEXT:    mul x10, x2, x7
; CHECK-SD-NEXT:    mul x6, x2, x0
; CHECK-SD-NEXT:    adds x0, x16, x8
; CHECK-SD-NEXT:    adc x1, x15, x9
; CHECK-SD-NEXT:    adds x9, x5, x4
; CHECK-SD-NEXT:    umulh x13, x2, x7
; CHECK-SD-NEXT:    adc x11, x17, x18
; CHECK-SD-NEXT:    cmn x10, x9
; CHECK-SD-NEXT:    asr x12, x11, #63
; CHECK-SD-NEXT:    mul x8, x3, x7
; CHECK-SD-NEXT:    smulh x9, x3, x7
; CHECK-SD-NEXT:    adc x10, x13, x6
; CHECK-SD-NEXT:    asr x13, x10, #63
; CHECK-SD-NEXT:    adds x10, x11, x10
; CHECK-SD-NEXT:    adc x11, x12, x13
; CHECK-SD-NEXT:    adds x2, x8, x10
; CHECK-SD-NEXT:    adc x3, x9, x11
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: smulh_v2i128:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    stp x22, x21, [sp, #-32]! // 16-byte Folded Spill
; CHECK-GI-NEXT:    asr x8, x1, #63
; CHECK-GI-NEXT:    asr x14, x5, #63
; CHECK-GI-NEXT:    umulh x15, x1, x5
; CHECK-GI-NEXT:    stp x20, x19, [sp, #16] // 16-byte Folded Spill
; CHECK-GI-NEXT:    umulh x12, x8, x4
; CHECK-GI-NEXT:    umulh x16, x0, x14
; CHECK-GI-NEXT:    umulh x9, x0, x4
; CHECK-GI-NEXT:    add x12, x12, x15
; CHECK-GI-NEXT:    mul x11, x0, x5
; CHECK-GI-NEXT:    add x12, x12, x16
; CHECK-GI-NEXT:    madd x12, x0, x14, x12
; CHECK-GI-NEXT:    mul x19, x0, x14
; CHECK-GI-NEXT:    adds x9, x9, x11
; CHECK-GI-NEXT:    madd x12, x1, x14, x12
; CHECK-GI-NEXT:    cset w11, hs
; CHECK-GI-NEXT:    and x11, x11, #0x1
; CHECK-GI-NEXT:    mul x10, x1, x4
; CHECK-GI-NEXT:    madd x14, x8, x5, x12
; CHECK-GI-NEXT:    asr x12, x3, #63
; CHECK-GI-NEXT:    umulh x13, x1, x4
; CHECK-GI-NEXT:    cmn x9, x10
; CHECK-GI-NEXT:    mul x18, x1, x5
; CHECK-GI-NEXT:    asr x1, x7, #63
; CHECK-GI-NEXT:    umulh x20, x0, x5
; CHECK-GI-NEXT:    umulh x0, x12, x6
; CHECK-GI-NEXT:    umulh x5, x3, x7
; CHECK-GI-NEXT:    umulh x21, x2, x1
; CHECK-GI-NEXT:    mul x17, x8, x4
; CHECK-GI-NEXT:    add x10, x0, x5
; CHECK-GI-NEXT:    cset w0, hs
; CHECK-GI-NEXT:    adds x13, x13, x20
; CHECK-GI-NEXT:    cset w5, hs
; CHECK-GI-NEXT:    adds x13, x13, x19
; CHECK-GI-NEXT:    umulh x15, x2, x6
; CHECK-GI-NEXT:    add x10, x10, x21
; CHECK-GI-NEXT:    cset w19, hs
; CHECK-GI-NEXT:    adds x13, x13, x18
; CHECK-GI-NEXT:    mul x16, x2, x7
; CHECK-GI-NEXT:    and x5, x5, #0x1
; CHECK-GI-NEXT:    and x19, x19, #0x1
; CHECK-GI-NEXT:    cset w18, hs
; CHECK-GI-NEXT:    add x5, x5, x19
; CHECK-GI-NEXT:    adds x13, x13, x17
; CHECK-GI-NEXT:    madd x10, x2, x1, x10
; CHECK-GI-NEXT:    and x17, x0, #0x1
; CHECK-GI-NEXT:    and x18, x18, #0x1
; CHECK-GI-NEXT:    add x11, x11, x17
; CHECK-GI-NEXT:    add x17, x5, x18
; CHECK-GI-NEXT:    cset w18, hs
; CHECK-GI-NEXT:    mul x22, x3, x6
; CHECK-GI-NEXT:    and x18, x18, #0x1
; CHECK-GI-NEXT:    adds x0, x13, x11
; CHECK-GI-NEXT:    add x13, x17, x18
; CHECK-GI-NEXT:    cset w17, hs
; CHECK-GI-NEXT:    adds x15, x15, x16
; CHECK-GI-NEXT:    umulh x9, x3, x6
; CHECK-GI-NEXT:    cset w16, hs
; CHECK-GI-NEXT:    and x17, x17, #0x1
; CHECK-GI-NEXT:    and x16, x16, #0x1
; CHECK-GI-NEXT:    add x13, x13, x17
; CHECK-GI-NEXT:    mul x20, x2, x1
; CHECK-GI-NEXT:    cmn x15, x22
; CHECK-GI-NEXT:    madd x10, x3, x1, x10
; CHECK-GI-NEXT:    cset w18, hs
; CHECK-GI-NEXT:    and x18, x18, #0x1
; CHECK-GI-NEXT:    umulh x1, x2, x7
; CHECK-GI-NEXT:    mul x11, x3, x7
; CHECK-GI-NEXT:    mul x15, x12, x6
; CHECK-GI-NEXT:    adds x9, x9, x1
; CHECK-GI-NEXT:    madd x10, x12, x7, x10
; CHECK-GI-NEXT:    cset w1, hs
; CHECK-GI-NEXT:    adds x9, x9, x20
; CHECK-GI-NEXT:    cset w2, hs
; CHECK-GI-NEXT:    adds x9, x9, x11
; CHECK-GI-NEXT:    and x1, x1, #0x1
; CHECK-GI-NEXT:    and x2, x2, #0x1
; CHECK-GI-NEXT:    madd x8, x8, x4, x14
; CHECK-GI-NEXT:    add x14, x16, x18
; CHECK-GI-NEXT:    cset w11, hs
; CHECK-GI-NEXT:    adds x9, x9, x15
; CHECK-GI-NEXT:    add x16, x1, x2
; CHECK-GI-NEXT:    madd x10, x12, x6, x10
; CHECK-GI-NEXT:    and x11, x11, #0x1
; CHECK-GI-NEXT:    cset w12, hs
; CHECK-GI-NEXT:    adds x2, x9, x14
; CHECK-GI-NEXT:    add x9, x16, x11
; CHECK-GI-NEXT:    and x11, x12, #0x1
; CHECK-GI-NEXT:    cset w12, hs
; CHECK-GI-NEXT:    add x9, x9, x11
; CHECK-GI-NEXT:    and x11, x12, #0x1
; CHECK-GI-NEXT:    ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-GI-NEXT:    add x9, x9, x11
; CHECK-GI-NEXT:    add x1, x8, x13
; CHECK-GI-NEXT:    add x3, x10, x9
; CHECK-GI-NEXT:    ldp x22, x21, [sp], #32 // 16-byte Folded Reload
; CHECK-GI-NEXT:    ret
  %r = call <2 x i128> @llvm.smulh(<2 x i128> %x, <2 x i128> %y)
  ret <2 x i128> %r
}