llvm/test/CodeGen/AArch64/neg-abs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-none-elf < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-elf -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI

declare i64 @llvm.abs.i64(i64, i1 immarg)

define i64 @neg_abs64(i64 %x) {
; CHECK-SD-LABEL: neg_abs64:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    cmp x0, #0
; CHECK-SD-NEXT:    cneg x0, x0, pl
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: neg_abs64:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    cmp x0, #0
; CHECK-GI-NEXT:    cneg x8, x0, le
; CHECK-GI-NEXT:    neg x0, x8
; CHECK-GI-NEXT:    ret
  %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
  %neg = sub nsw i64 0, %abs
  ret i64 %neg
}

declare i32 @llvm.abs.i32(i32, i1 immarg)

define i32 @neg_abs32(i32 %x) {
; CHECK-SD-LABEL: neg_abs32:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    cmp w0, #0
; CHECK-SD-NEXT:    cneg w0, w0, pl
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: neg_abs32:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    cmp w0, #0
; CHECK-GI-NEXT:    cneg w8, w0, le
; CHECK-GI-NEXT:    neg w0, w8
; CHECK-GI-NEXT:    ret
  %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
  %neg = sub nsw i32 0, %abs
  ret i32 %neg
}

declare i16 @llvm.abs.i16(i16, i1 immarg)

define i16 @neg_abs16(i16 %x) {
; CHECK-SD-LABEL: neg_abs16:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    sbfx w8, w0, #15, #1
; CHECK-SD-NEXT:    eor w9, w0, w8
; CHECK-SD-NEXT:    sub w0, w8, w9
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: neg_abs16:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    sxth w8, w0
; CHECK-GI-NEXT:    cmp w8, #0
; CHECK-GI-NEXT:    cneg w8, w0, le
; CHECK-GI-NEXT:    neg w0, w8
; CHECK-GI-NEXT:    ret
  %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
  %neg = sub nsw i16 0, %abs
  ret i16 %neg
}


declare i128 @llvm.abs.i128(i128, i1 immarg)

define i128 @neg_abs128(i128 %x) {
; CHECK-SD-LABEL: neg_abs128:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    asr x8, x1, #63
; CHECK-SD-NEXT:    eor x9, x0, x8
; CHECK-SD-NEXT:    eor x10, x1, x8
; CHECK-SD-NEXT:    subs x0, x8, x9
; CHECK-SD-NEXT:    sbc x1, x8, x10
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: neg_abs128:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    asr x8, x1, #63
; CHECK-GI-NEXT:    adds x9, x0, x8
; CHECK-GI-NEXT:    adc x10, x1, x8
; CHECK-GI-NEXT:    eor x9, x9, x8
; CHECK-GI-NEXT:    eor x8, x10, x8
; CHECK-GI-NEXT:    negs x0, x9
; CHECK-GI-NEXT:    ngc x1, x8
; CHECK-GI-NEXT:    ret
  %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
  %neg = sub nsw i128 0, %abs
  ret i128 %neg
}



define i64 @abs64(i64 %x) {
; CHECK-SD-LABEL: abs64:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    cmp x0, #0
; CHECK-SD-NEXT:    cneg x0, x0, mi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abs64:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    cmp x0, #0
; CHECK-GI-NEXT:    cneg x0, x0, le
; CHECK-GI-NEXT:    ret
  %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
  ret i64 %abs
}

define i32 @abs32(i32 %x) {
; CHECK-SD-LABEL: abs32:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    cmp w0, #0
; CHECK-SD-NEXT:    cneg w0, w0, mi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abs32:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    cmp w0, #0
; CHECK-GI-NEXT:    cneg w0, w0, le
; CHECK-GI-NEXT:    ret
  %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
  ret i32 %abs
}

define i16 @abs16(i16 %x) {
; CHECK-SD-LABEL: abs16:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    sxth w8, w0
; CHECK-SD-NEXT:    cmp w8, #0
; CHECK-SD-NEXT:    cneg w0, w8, mi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abs16:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    sxth w8, w0
; CHECK-GI-NEXT:    cmp w8, #0
; CHECK-GI-NEXT:    cneg w0, w0, le
; CHECK-GI-NEXT:    ret
  %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
  ret i16 %abs
}

define i128 @abs128(i128 %x) {
; CHECK-SD-LABEL: abs128:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    asr x8, x1, #63
; CHECK-SD-NEXT:    eor x9, x0, x8
; CHECK-SD-NEXT:    eor x10, x1, x8
; CHECK-SD-NEXT:    subs x0, x9, x8
; CHECK-SD-NEXT:    sbc x1, x10, x8
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: abs128:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    asr x8, x1, #63
; CHECK-GI-NEXT:    adds x9, x0, x8
; CHECK-GI-NEXT:    adc x10, x1, x8
; CHECK-GI-NEXT:    eor x0, x9, x8
; CHECK-GI-NEXT:    eor x1, x10, x8
; CHECK-GI-NEXT:    ret
  %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
  ret i128 %abs
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}