llvm/test/CodeGen/AArch64/cmpbr-ccmp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=arm64-apple-ios -mattr=+cmpbr -run-pass=aarch64-ccmp -aarch64-stress-ccmp -verify-machineinstrs -simplify-mir -o - %s | FileCheck %s

---
name:            cc_eq
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_eq
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 4, 1, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 0, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 0, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 0, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cc_ne
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_ne
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 0, 0, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 1, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 1, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 1, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cc_hs
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_hs
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 2, 3, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 2, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 2, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 2, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cc_lo
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_lo
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 0, 2, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 3, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 3, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 3, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cc_hi
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_hi
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 2, 9, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 8, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 8, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 8, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cc_ls
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_ls
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 0, 8, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 9, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 9, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 9, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cc_ge
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_ge
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 0, 11, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 10, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 10, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 10, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cc_lt
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_lt
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 8, 10, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 11, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 11, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 11, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cc_gt
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_gt
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 0, 13, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 12, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 12, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 12, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cc_le
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_le
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 4, 12, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 13, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 13, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 13, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cc_mixed_lo_gt
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cc_mixed_lo_gt
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 0, 2, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 12, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 3, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 12, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            head_targets_cmpbb
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: head_targets_cmpbb
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 0, 10, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 12, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 10, %0, %1, %bb.1
    B %bb.3

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 12, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cbb_chain
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cbb_chain
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 4, 1, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 0, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBBAssertExt 0, %0, %1, %bb.3, -1, -1
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBBAssertExt 0, %2, %3, %bb.3, -1, -1
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cbh_chain
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cbh_chain
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   $wzr = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 0, 0, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 1, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBHAssertExt 1, %0, %1, %bb.3, -1, -1
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBHAssertExt 1, %2, %3, %bb.3, -1, -1
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cbb_head_zext
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cbb_head_zext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   [[ANDWri:%[0-9]+]]:gpr32common = ANDWri [[COPY]], 7
  ; CHECK-NEXT:   $wzr = SUBSWrx [[ANDWri]], [[COPY1]], 0, implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 0, 3, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 12, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBBAssertExt 2, %0, %1, %bb.3, 0, 0
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 12, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cbh_head_sext
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cbh_head_sext
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.3(0x60000000), %bb.2(0x20000000)
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   [[SBFMWri:%[0-9]+]]:gpr32common = SBFMWri [[COPY]], 0, 15
  ; CHECK-NEXT:   $wzr = SUBSWrx [[SBFMWri]], [[COPY1]], 40, implicit-def $nzcv
  ; CHECK-NEXT:   CCMPWr [[COPY2]], [[COPY3]], 0, 13, implicit-def $nzcv, implicit $nzcv
  ; CHECK-NEXT:   Bcc 10, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBHAssertExt 12, %0, %1, %bb.3, 5, 5
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBWPrr 10, %2, %3, %bb.3
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cbb_cmpbb_sext_reject
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cbb_cmpbb_sext_reject
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1, %bb.3
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   CBWPrr 0, [[COPY]], [[COPY1]], %bb.3
  ; CHECK-NEXT:   B %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2, %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   CBBAssertExt 1, [[COPY2]], [[COPY3]], %bb.3, 4, 4
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 0, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBBAssertExt 1, %2, %3, %bb.3, 4, 4
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...

---
name:            cbh_cmpbb_zext_reject
alignment:       4
tracksRegLiveness: true
isSSA:           true
registers:
  - { id: 0, class: gpr32 }
  - { id: 1, class: gpr32 }
  - { id: 2, class: gpr32 }
  - { id: 3, class: gpr32 }
  - { id: 4, class: gpr32 }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$w1', virtual-reg: '%1' }
  - { reg: '$w2', virtual-reg: '%2' }
  - { reg: '$w3', virtual-reg: '%3' }
body:             |
  ; CHECK-LABEL: name: cbh_cmpbb_zext_reject
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1, %bb.3
  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
  ; CHECK-NEXT:   CBWPrr 0, [[COPY]], [[COPY1]], %bb.3
  ; CHECK-NEXT:   B %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2, %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   CBHAssertExt 8, [[COPY2]], [[COPY3]], %bb.3, 1, 1
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7
  ; CHECK-NEXT:   $w0 = COPY [[MOVi32imm]]
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    successors: %bb.1, %bb.3
    liveins: $w0, $w1, $w2, $w3

    %0:gpr32 = COPY $w0
    %1:gpr32 = COPY $w1
    %2:gpr32 = COPY $w2
    %3:gpr32 = COPY $w3
    CBWPrr 0, %0, %1, %bb.3
    B %bb.1

  bb.1:
    successors: %bb.2, %bb.3

    CBHAssertExt 8, %2, %3, %bb.3, 1, 1
    B %bb.2

  bb.2:
    successors: %bb.3

    B %bb.3

  bb.3:
    %4:gpr32 = MOVi32imm 7
    $w0 = COPY %4
    RET_ReallyLR implicit $w0
...