llvm/test/CodeGen/AArch64/binopshuffles.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
; RUN: llc -mtriple=aarch64-linux-gnu --lower-interleaved-accesses=false < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED

define <4 x float> @vld2(ptr %pSrc) {
; CHECK-IAENABLED-LABEL: vld2:
; CHECK-IAENABLED:       // %bb.0: // %entry
; CHECK-IAENABLED-NEXT:    ld2 { v1.4s, v2.4s }, [x0]
; CHECK-IAENABLED-NEXT:    fmul v0.4s, v1.4s, v1.4s
; CHECK-IAENABLED-NEXT:    fmla v0.4s, v2.4s, v2.4s
; CHECK-IAENABLED-NEXT:    ret
;
; CHECK-IADISABLED-LABEL: vld2:
; CHECK-IADISABLED:       // %bb.0: // %entry
; CHECK-IADISABLED-NEXT:    ldp q0, q1, [x0]
; CHECK-IADISABLED-NEXT:    fmul v1.4s, v1.4s, v1.4s
; CHECK-IADISABLED-NEXT:    fmul v0.4s, v0.4s, v0.4s
; CHECK-IADISABLED-NEXT:    faddp v0.4s, v0.4s, v1.4s
; CHECK-IADISABLED-NEXT:    ret
entry:
  %wide.vec = load <8 x float>, ptr %pSrc, align 4
  %l2 = fmul fast <8 x float> %wide.vec, %wide.vec
  %l3 = shufflevector <8 x float> %l2, <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %l4 = fmul fast <8 x float> %wide.vec, %wide.vec
  %l5 = shufflevector <8 x float> %l4, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %l6 = fadd fast <4 x float> %l5, %l3
  ret <4 x float> %l6
}

define <4 x float> @vld3(ptr %pSrc) {
; CHECK-IAENABLED-LABEL: vld3:
; CHECK-IAENABLED:       // %bb.0: // %entry
; CHECK-IAENABLED-NEXT:    ld3 { v1.4s, v2.4s, v3.4s }, [x0]
; CHECK-IAENABLED-NEXT:    fmul v0.4s, v1.4s, v1.4s
; CHECK-IAENABLED-NEXT:    fmla v0.4s, v2.4s, v2.4s
; CHECK-IAENABLED-NEXT:    fmla v0.4s, v3.4s, v3.4s
; CHECK-IAENABLED-NEXT:    ret
;
; CHECK-IADISABLED-LABEL: vld3:
; CHECK-IADISABLED:       // %bb.0: // %entry
; CHECK-IADISABLED-NEXT:    ldp q0, q1, [x0]
; CHECK-IADISABLED-NEXT:    ldr q4, [x0, #32]
; CHECK-IADISABLED-NEXT:    fmul v4.4s, v4.4s, v4.4s
; CHECK-IADISABLED-NEXT:    fmul v0.4s, v0.4s, v0.4s
; CHECK-IADISABLED-NEXT:    fmul v1.4s, v1.4s, v1.4s
; CHECK-IADISABLED-NEXT:    mov v2.16b, v0.16b
; CHECK-IADISABLED-NEXT:    rev64 v3.4s, v1.4s
; CHECK-IADISABLED-NEXT:    mov v2.s[1], v0.s[3]
; CHECK-IADISABLED-NEXT:    mov v3.s[0], v0.s[1]
; CHECK-IADISABLED-NEXT:    mov v2.s[2], v1.s[2]
; CHECK-IADISABLED-NEXT:    mov v1.s[0], v0.s[2]
; CHECK-IADISABLED-NEXT:    mov v3.s[3], v4.s[2]
; CHECK-IADISABLED-NEXT:    mov v2.s[3], v4.s[1]
; CHECK-IADISABLED-NEXT:    mov v1.s[2], v4.s[0]
; CHECK-IADISABLED-NEXT:    fadd v0.4s, v3.4s, v2.4s
; CHECK-IADISABLED-NEXT:    mov v1.s[3], v4.s[3]
; CHECK-IADISABLED-NEXT:    fadd v0.4s, v0.4s, v1.4s
; CHECK-IADISABLED-NEXT:    ret
entry:
  %wide.vec = load <12 x float>, ptr %pSrc, align 4
  %l2 = fmul fast <12 x float> %wide.vec, %wide.vec
  %l3 = shufflevector <12 x float> %l2, <12 x float> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
  %l4 = fmul fast <12 x float> %wide.vec, %wide.vec
  %l5 = shufflevector <12 x float> %l4, <12 x float> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
  %l6 = fadd fast <4 x float> %l5, %l3
  %l7 = fmul fast <12 x float> %wide.vec, %wide.vec
  %l8 = shufflevector <12 x float> %l7, <12 x float> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
  %l9 = fadd fast <4 x float> %l6, %l8
  ret <4 x float> %l9
}

define <4 x float> @vld4(ptr %pSrc) {
; CHECK-IAENABLED-LABEL: vld4:
; CHECK-IAENABLED:       // %bb.0: // %entry
; CHECK-IAENABLED-NEXT:    ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x0]
; CHECK-IAENABLED-NEXT:    fmul v0.4s, v3.4s, v3.4s
; CHECK-IAENABLED-NEXT:    fmla v0.4s, v4.4s, v4.4s
; CHECK-IAENABLED-NEXT:    ret
;
; CHECK-IADISABLED-LABEL: vld4:
; CHECK-IADISABLED:       // %bb.0: // %entry
; CHECK-IADISABLED-NEXT:    ldp q0, q1, [x0]
; CHECK-IADISABLED-NEXT:    ldp q2, q3, [x0, #32]
; CHECK-IADISABLED-NEXT:    fmul v1.4s, v1.4s, v1.4s
; CHECK-IADISABLED-NEXT:    fmul v0.4s, v0.4s, v0.4s
; CHECK-IADISABLED-NEXT:    fmul v3.4s, v3.4s, v3.4s
; CHECK-IADISABLED-NEXT:    fmul v2.4s, v2.4s, v2.4s
; CHECK-IADISABLED-NEXT:    uzp2 v4.4s, v0.4s, v1.4s
; CHECK-IADISABLED-NEXT:    zip2 v1.4s, v0.4s, v1.4s
; CHECK-IADISABLED-NEXT:    trn1 v5.4s, v2.4s, v3.4s
; CHECK-IADISABLED-NEXT:    zip2 v2.4s, v2.4s, v3.4s
; CHECK-IADISABLED-NEXT:    uzp2 v0.4s, v4.4s, v0.4s
; CHECK-IADISABLED-NEXT:    mov v1.d[1], v5.d[1]
; CHECK-IADISABLED-NEXT:    mov v0.d[1], v2.d[1]
; CHECK-IADISABLED-NEXT:    fadd v0.4s, v0.4s, v1.4s
; CHECK-IADISABLED-NEXT:    ret
entry:
  %wide.vec = load <16 x float>, ptr %pSrc, align 4
  %l3 = fmul fast <16 x float> %wide.vec, %wide.vec
  %l4 = shufflevector <16 x float> %l3, <16 x float> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
  %l5 = fmul fast <16 x float> %wide.vec, %wide.vec
  %l6 = shufflevector <16 x float> %l5, <16 x float> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
  %l7 = fadd fast <4 x float> %l6, %l4
  %l8 = fmul fast <16 x float> %wide.vec, %wide.vec
  %l9 = shufflevector <16 x float> %l8, <16 x float> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
  %l10 = fmul fast <16 x float> %wide.vec, %wide.vec
  %l11 = shufflevector <16 x float> %l10, <16 x float> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
  %l12 = fadd fast <4 x float> %l11, %l9
  ret <4 x float> %l12
}

define <4 x float> @twosrc(ptr %pSrc1, ptr %pSrc2) {
; CHECK-IAENABLED-LABEL: twosrc:
; CHECK-IAENABLED:       // %bb.0: // %entry
; CHECK-IAENABLED-NEXT:    ld2 { v1.4s, v2.4s }, [x0]
; CHECK-IAENABLED-NEXT:    ld2 { v3.4s, v4.4s }, [x1]
; CHECK-IAENABLED-NEXT:    fmul v0.4s, v3.4s, v1.4s
; CHECK-IAENABLED-NEXT:    fmla v0.4s, v2.4s, v4.4s
; CHECK-IAENABLED-NEXT:    ret
;
; CHECK-IADISABLED-LABEL: twosrc:
; CHECK-IADISABLED:       // %bb.0: // %entry
; CHECK-IADISABLED-NEXT:    ldp q0, q1, [x0]
; CHECK-IADISABLED-NEXT:    ldp q2, q3, [x1]
; CHECK-IADISABLED-NEXT:    fmul v1.4s, v3.4s, v1.4s
; CHECK-IADISABLED-NEXT:    fmul v0.4s, v2.4s, v0.4s
; CHECK-IADISABLED-NEXT:    faddp v0.4s, v0.4s, v1.4s
; CHECK-IADISABLED-NEXT:    ret
entry:
  %wide.vec = load <8 x float>, ptr %pSrc1, align 4
  %wide.vec26 = load <8 x float>, ptr %pSrc2, align 4
  %l4 = fmul fast <8 x float> %wide.vec26, %wide.vec
  %l5 = shufflevector <8 x float> %l4, <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %l6 = fmul fast <8 x float> %wide.vec26, %wide.vec
  %l7 = shufflevector <8 x float> %l6, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %l8 = fadd fast <4 x float> %l7, %l5
  ret <4 x float> %l8
}

define <4 x float> @twosrc2(ptr %pSrc1, ptr %pSrc2) {
; CHECK-IAENABLED-LABEL: twosrc2:
; CHECK-IAENABLED:       // %bb.0: // %entry
; CHECK-IAENABLED-NEXT:    ld2 { v1.4s, v2.4s }, [x0]
; CHECK-IAENABLED-NEXT:    ld2 { v3.4s, v4.4s }, [x1]
; CHECK-IAENABLED-NEXT:    fmul v0.4s, v3.4s, v1.4s
; CHECK-IAENABLED-NEXT:    fmla v0.4s, v2.4s, v4.4s
; CHECK-IAENABLED-NEXT:    ret
;
; CHECK-IADISABLED-LABEL: twosrc2:
; CHECK-IADISABLED:       // %bb.0: // %entry
; CHECK-IADISABLED-NEXT:    ldp q1, q2, [x0]
; CHECK-IADISABLED-NEXT:    ldp q3, q4, [x1]
; CHECK-IADISABLED-NEXT:    fmul v0.4s, v4.4s, v2.4s
; CHECK-IADISABLED-NEXT:    fmul v5.4s, v3.4s, v1.4s
; CHECK-IADISABLED-NEXT:    uzp2 v3.4s, v3.4s, v4.4s
; CHECK-IADISABLED-NEXT:    uzp2 v1.4s, v1.4s, v2.4s
; CHECK-IADISABLED-NEXT:    uzp1 v0.4s, v5.4s, v0.4s
; CHECK-IADISABLED-NEXT:    fmla v0.4s, v1.4s, v3.4s
; CHECK-IADISABLED-NEXT:    ret
entry:
  %wide.vec = load <8 x float>, ptr %pSrc1, align 4
  %wide.vec26 = load <8 x float>, ptr %pSrc2, align 4
  %l4 = fmul fast <8 x float> %wide.vec26, %wide.vec
  %l5 = shufflevector <8 x float> %l4, <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %s1 = shufflevector <8 x float> %wide.vec26, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %s2 = shufflevector <8 x float> %wide.vec, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %l6 = fmul fast <4 x float> %s1, %s2
  %l8 = fadd fast <4 x float> %l6, %l5
  ret <4 x float> %l8
}

define void @noncanonical(ptr %p0, ptr %p1, ptr %p2) {
; CHECK-LABEL: noncanonical:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldr d0, [x1]
; CHECK-NEXT:    xtn v0.8b, v0.8h
; CHECK-NEXT:    str s0, [x2]
; CHECK-NEXT:    ret
entry:
  %v0 = load <8 x i8>, ptr %p0
  %v1 = add <8 x i8> %v0, <i8 0, i8 1, i8 2, i8 3, i8 7, i8 7, i8 7, i8 7>
  %v2 = load <8 x i8>, ptr %p1
  %shuffled = shufflevector <8 x i8> %v2, <8 x i8> %v1, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  store <4 x i8> %shuffled, ptr %p2
  ret void
}

define void @noncanonical2(ptr %p0, ptr %p1, ptr %p2) {
; CHECK-LABEL: noncanonical2:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ret
entry:
  %v0 = load <8 x i8>, ptr %p0
  %v1 = load <8 x i8>, ptr %p1
  %v2 = add <8 x i8> %v0, %v1
  %shuffled = shufflevector <8 x i8> poison, <8 x i8> %v2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  store <4 x i8> %shuffled, ptr %p2
  ret void
}

define <4 x float> @noncanonical3(ptr %pSrc) {
; CHECK-LABEL: noncanonical3:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldp q0, q1, [x0]
; CHECK-NEXT:    fmul v1.4s, v1.4s, v1.4s
; CHECK-NEXT:    fmul v0.4s, v0.4s, v0.4s
; CHECK-NEXT:    faddp v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
entry:
  %wide.vec = load <8 x float>, ptr %pSrc, align 4
  %l2 = fmul fast <8 x float> %wide.vec, %wide.vec
  %l3 = shufflevector <8 x float> poison, <8 x float> %l2, <4 x i32> <i32 8, i32 10, i32 12, i32 14>
  %l4 = fmul fast <8 x float> %wide.vec, %wide.vec
  %l5 = shufflevector <8 x float> %l4, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %l6 = fadd fast <4 x float> %l5, %l3
  ret <4 x float> %l6
}

define void @noncanonical_extmask(ptr %p0, ptr %p1, ptr %p2) {
; CHECK-LABEL: noncanonical_extmask:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    adrp x8, .LCPI8_0
; CHECK-NEXT:    ldr d0, [x0]
; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI8_0]
; CHECK-NEXT:    add v0.8b, v0.8b, v1.8b
; CHECK-NEXT:    ldr d1, [x1]
; CHECK-NEXT:    uzp1 v0.8b, v1.8b, v0.8b
; CHECK-NEXT:    str d0, [x2]
; CHECK-NEXT:    ret
entry:
  %v0 = load <8 x i8>, ptr %p0
  %v1 = add <8 x i8> %v0, <i8 0, i8 1, i8 2, i8 3, i8 7, i8 7, i8 7, i8 7>
  %v2 = load <8 x i8>, ptr %p1
  %shuffled = shufflevector <8 x i8> %v2, <8 x i8> %v1, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
  store <8 x i8> %shuffled, ptr %p2
  ret void
}

define void @skip_optimizing_dead_binop(ptr %p0, ptr %p1) {
; CHECK-LABEL: skip_optimizing_dead_binop:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ret
entry:
  %v0 = load <8 x double>, ptr %p0
  %shuffled_1 = shufflevector <8 x double> %v0, <8 x double> poison, <2 x i32> <i32 0, i32 4>
  %shuffled_2 = shufflevector <8 x double> %v0, <8 x double> poison, <2 x i32> <i32 1, i32 5>
  %shuffled_3 = shufflevector <8 x double> %v0, <8 x double> poison, <2 x i32> <i32 2, i32 6>
  %shuffled_4 = shufflevector <8 x double> %v0, <8 x double> poison, <2 x i32> <i32 3, i32 7>
  %dead_binop = fadd <8 x double> %v0, %v0
  ret void
}

define <4 x float> @twosrc_intrinsic(ptr %pSrc1, ptr %pSrc2) {
; CHECK-IAENABLED-LABEL: twosrc_intrinsic:
; CHECK-IAENABLED:       // %bb.0: // %entry
; CHECK-IAENABLED-NEXT:    ld2 { v1.4s, v2.4s }, [x0]
; CHECK-IAENABLED-NEXT:    ld2 { v3.4s, v4.4s }, [x1]
; CHECK-IAENABLED-NEXT:    fmul v0.4s, v3.4s, v1.4s
; CHECK-IAENABLED-NEXT:    fmla v0.4s, v2.4s, v4.4s
; CHECK-IAENABLED-NEXT:    ret
;
; CHECK-IADISABLED-LABEL: twosrc_intrinsic:
; CHECK-IADISABLED:       // %bb.0: // %entry
; CHECK-IADISABLED-NEXT:    ldp q1, q0, [x0]
; CHECK-IADISABLED-NEXT:    ldp q3, q2, [x1]
; CHECK-IADISABLED-NEXT:    uzp1 v4.4s, v1.4s, v0.4s
; CHECK-IADISABLED-NEXT:    uzp2 v1.4s, v1.4s, v0.4s
; CHECK-IADISABLED-NEXT:    uzp1 v5.4s, v3.4s, v2.4s
; CHECK-IADISABLED-NEXT:    uzp2 v2.4s, v3.4s, v2.4s
; CHECK-IADISABLED-NEXT:    fmul v0.4s, v5.4s, v4.4s
; CHECK-IADISABLED-NEXT:    fmla v0.4s, v1.4s, v2.4s
; CHECK-IADISABLED-NEXT:    ret
entry:
  %intrinsic.load.0 = load <8 x float>, ptr %pSrc1, align 4
  %ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
  %0 = extractvalue { <4 x float>, <4 x float> } %ldN, 1
  %1 = extractvalue { <4 x float>, <4 x float> } %ldN, 0
  %intrinsic.load.1 = load <8 x float>, ptr %pSrc2, align 4
  %ldN7 = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.1)
  %2 = extractvalue { <4 x float>, <4 x float> } %ldN7, 0
  %3 = extractvalue { <4 x float>, <4 x float> } %ldN7, 1
  %l46 = fmul fast <4 x float> %2, %1
  %l63 = fmul fast <4 x float> %3, %0
  %l8 = fadd fast <4 x float> %l63, %l46
  ret <4 x float> %l8
}

define <4 x float> @twosrc2_intrinsic(ptr %pSrc1, ptr %pSrc2) {
; CHECK-IAENABLED-LABEL: twosrc2_intrinsic:
; CHECK-IAENABLED:       // %bb.0: // %entry
; CHECK-IAENABLED-NEXT:    ld2 { v1.4s, v2.4s }, [x0]
; CHECK-IAENABLED-NEXT:    ld2 { v3.4s, v4.4s }, [x1]
; CHECK-IAENABLED-NEXT:    fmul v0.4s, v3.4s, v1.4s
; CHECK-IAENABLED-NEXT:    fmla v0.4s, v2.4s, v4.4s
; CHECK-IAENABLED-NEXT:    ret
;
; CHECK-IADISABLED-LABEL: twosrc2_intrinsic:
; CHECK-IADISABLED:       // %bb.0: // %entry
; CHECK-IADISABLED-NEXT:    ldp q1, q0, [x0]
; CHECK-IADISABLED-NEXT:    ldp q3, q2, [x1]
; CHECK-IADISABLED-NEXT:    uzp1 v4.4s, v1.4s, v0.4s
; CHECK-IADISABLED-NEXT:    uzp2 v1.4s, v1.4s, v0.4s
; CHECK-IADISABLED-NEXT:    uzp1 v5.4s, v3.4s, v2.4s
; CHECK-IADISABLED-NEXT:    uzp2 v2.4s, v3.4s, v2.4s
; CHECK-IADISABLED-NEXT:    fmul v0.4s, v5.4s, v4.4s
; CHECK-IADISABLED-NEXT:    fmla v0.4s, v1.4s, v2.4s
; CHECK-IADISABLED-NEXT:    ret
entry:
  %intrinsic.load.0 = load <8 x float>, ptr %pSrc1, align 4
  %ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
  %0 = extractvalue { <4 x float>, <4 x float> } %ldN, 1
  %1 = extractvalue { <4 x float>, <4 x float> } %ldN, 0
  %intrinsic.load.1 = load <8 x float>, ptr %pSrc2, align 4
  %ldN4 = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.1)
  %2 = extractvalue { <4 x float>, <4 x float> } %ldN4, 0
  %3 = extractvalue { <4 x float>, <4 x float> } %ldN4, 1
  %l43 = fmul fast <4 x float> %2, %1
  %l6 = fmul fast <4 x float> %3, %0
  %l8 = fadd fast <4 x float> %l6, %l43
  ret <4 x float> %l8
}

define <4 x float> @vld2_intrinsic(ptr %pSrc) {
; CHECK-IAENABLED-LABEL: vld2_intrinsic:
; CHECK-IAENABLED:       // %bb.0: // %entry
; CHECK-IAENABLED-NEXT:    ld2 { v1.4s, v2.4s }, [x0]
; CHECK-IAENABLED-NEXT:    fmul v0.4s, v1.4s, v1.4s
; CHECK-IAENABLED-NEXT:    fmla v0.4s, v2.4s, v2.4s
; CHECK-IAENABLED-NEXT:    ret
;
; CHECK-IADISABLED-LABEL: vld2_intrinsic:
; CHECK-IADISABLED:       // %bb.0: // %entry
; CHECK-IADISABLED-NEXT:    ldp q1, q0, [x0]
; CHECK-IADISABLED-NEXT:    uzp1 v2.4s, v1.4s, v0.4s
; CHECK-IADISABLED-NEXT:    uzp2 v1.4s, v1.4s, v0.4s
; CHECK-IADISABLED-NEXT:    fmul v0.4s, v2.4s, v2.4s
; CHECK-IADISABLED-NEXT:    fmla v0.4s, v1.4s, v1.4s
; CHECK-IADISABLED-NEXT:    ret
entry:
  %intrinsic.load.0 = load <8 x float>, ptr %pSrc, align 4
  %ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
  %0 = extractvalue { <4 x float>, <4 x float> } %ldN, 1
  %1 = extractvalue { <4 x float>, <4 x float> } %ldN, 1
  %2 = extractvalue { <4 x float>, <4 x float> } %ldN, 0
  %3 = extractvalue { <4 x float>, <4 x float> } %ldN, 0
  %l26 = fmul fast <4 x float> %2, %3
  %l43 = fmul fast <4 x float> %0, %1
  %l6 = fadd fast <4 x float> %l43, %l26
  ret <4 x float> %l6
}

define <4 x float> @vld3_intrinsic(ptr %pSrc) {
; CHECK-LABEL: vld3_intrinsic:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ld3 { v1.4s, v2.4s, v3.4s }, [x0]
; CHECK-NEXT:    fmul v0.4s, v1.4s, v1.4s
; CHECK-NEXT:    fmla v0.4s, v2.4s, v2.4s
; CHECK-NEXT:    fmla v0.4s, v3.4s, v3.4s
; CHECK-NEXT:    ret
entry:
  %intrinsic.load.0 = load <12 x float>, ptr %pSrc, align 4
  %ldN = call { <4 x float>, <4 x float>, <4 x float> } @llvm.vector.deinterleave3.v12f32(<12 x float> %intrinsic.load.0)
  %0 = extractvalue { <4 x float>, <4 x float>, <4 x float> } %ldN, 2
  %1 = extractvalue { <4 x float>, <4 x float>, <4 x float> } %ldN, 2
  %2 = extractvalue { <4 x float>, <4 x float>, <4 x float> } %ldN, 1
  %3 = extractvalue { <4 x float>, <4 x float>, <4 x float> } %ldN, 1
  %4 = extractvalue { <4 x float>, <4 x float>, <4 x float> } %ldN, 0
  %5 = extractvalue { <4 x float>, <4 x float>, <4 x float> } %ldN, 0
  %l29 = fmul fast <4 x float> %4, %5
  %l46 = fmul fast <4 x float> %2, %3
  %l6 = fadd fast <4 x float> %l46, %l29
  %l73 = fmul fast <4 x float> %0, %1
  %l9 = fadd fast <4 x float> %l6, %l73
  ret <4 x float> %l9
}

define <4 x float> @vld4_intrinsic(ptr %pSrc) {
; CHECK-LABEL: vld4_intrinsic:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ld4 { v1.4s, v2.4s, v3.4s, v4.4s }, [x0]
; CHECK-NEXT:    fmul v0.4s, v3.4s, v3.4s
; CHECK-NEXT:    fmla v0.4s, v4.4s, v4.4s
; CHECK-NEXT:    ret
entry:
  %intrinsic.load.0 = load <16 x float>, ptr %pSrc, align 4
  %ldN = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.vector.deinterleave4.v16f32(<16 x float> %intrinsic.load.0)
  %0 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ldN, 3
  %1 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ldN, 3
  %2 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ldN, 2
  %3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ldN, 2
  %4 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ldN, 1
  %5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ldN, 1
  %6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ldN, 0
  %7 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ldN, 0
  %l312 = fmul fast <4 x float> %6, %7
  %l59 = fmul fast <4 x float> %4, %5
  %l7 = fadd fast <4 x float> %l59, %l312
  %l86 = fmul fast <4 x float> %2, %3
  %l103 = fmul fast <4 x float> %0, %1
  %l12 = fadd fast <4 x float> %l103, %l86
  ret <4 x float> %l12
}