clang/test/CodeGen/builtin-clear-padding-codegen.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
// RUN: %clang_cc1 -std=c11 -triple=x86_64-linux-gnu -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK64,CHECK64-LE,ITANIUM64,ITANIUM64-LE,LINUX
// RUN: %clang_cc1 -std=c11 -triple=x86_64-pc-windows-msvc -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK64,CHECK64-LE,WINDOWS
// RUN: %clang_cc1 -std=c11 -triple=armv7a-none-eabi -emit-llvm -o - %s | FileCheck %s --check-prefixes=ARM,ARM-LE
// RUN: %clang_cc1 -std=c11 -triple=armebv7a-none-eabi -emit-llvm -o - %s | FileCheck %s --check-prefixes=ARM,ARM-BE
// RUN: %clang_cc1 -std=c11 -triple=aarch64-none-eabi -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK64,CHECK64-LE,ITANIUM64,ITANIUM64-LE,AARCH64
// RUN: %clang_cc1 -std=c11 -triple=aarch64_be-none-eabi -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK64,ITANIUM64,AARCH64,AARCH64-BE

struct Empty {};

// ITANIUM64-LABEL: define dso_local void @testEmpty(
// ITANIUM64-SAME: ptr noundef [[E:%.*]]) #[[ATTR0:[0-9]+]] {
// ITANIUM64-NEXT:  [[ENTRY:.*:]]
// ITANIUM64-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 8
// ITANIUM64-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 8
// ITANIUM64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 8
// ITANIUM64-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testEmpty(
// WINDOWS-SAME: ptr noundef [[E:%.*]]) #[[ATTR0:[0-9]+]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// WINDOWS-NEXT:    store i8 0, ptr [[TMP1]], align 1
// WINDOWS-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    store i8 0, ptr [[TMP2]], align 1
// WINDOWS-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP3]], align 1
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP4]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testEmpty(
// ARM-SAME: ptr noundef [[E:%.*]]) #[[ATTR0:[0-9]+]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[E_ADDR]], align 4
// ARM-NEXT:    ret void
//
void testEmpty(struct Empty *e) {
  // Emtpy struct is empty in C in Itanium ABI, no padding
  // Emtpy struct has 4 bytes in C in clang's MSVC ABI
  __builtin_clear_padding(e);
}


// CHECK64-LABEL: define dso_local void @testPrimitiveNoPadding(
// CHECK64-SAME: ptr noundef [[I:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testPrimitiveNoPadding(
// ARM-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 4
// ARM-NEXT:    ret void
//
void testPrimitiveNoPadding(int *i) {
  // This should not clear any padding, since int has no padding.
  __builtin_clear_padding(i);
}


// LINUX-LABEL: define dso_local void @testPrimitiveLongDouble(
// LINUX-SAME: ptr noundef [[LD:%.*]]) #[[ATTR0]] {
// LINUX-NEXT:  [[ENTRY:.*:]]
// LINUX-NEXT:    [[LD_ADDR:%.*]] = alloca ptr, align 8
// LINUX-NEXT:    store ptr [[LD]], ptr [[LD_ADDR]], align 8
// LINUX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8
// LINUX-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// LINUX-NEXT:    store i8 0, ptr [[TMP1]], align 2
// LINUX-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// LINUX-NEXT:    store i8 0, ptr [[TMP2]], align 1
// LINUX-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// LINUX-NEXT:    store i8 0, ptr [[TMP3]], align 4
// LINUX-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// LINUX-NEXT:    store i8 0, ptr [[TMP4]], align 1
// LINUX-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// LINUX-NEXT:    store i8 0, ptr [[TMP5]], align 2
// LINUX-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// LINUX-NEXT:    store i8 0, ptr [[TMP6]], align 1
// LINUX-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testPrimitiveLongDouble(
// WINDOWS-SAME: ptr noundef [[LD:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[LD_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[LD]], ptr [[LD_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8
// WINDOWS-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testPrimitiveLongDouble(
// ARM-SAME: ptr noundef [[LD:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[LD_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[LD]], ptr [[LD_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 4
// ARM-NEXT:    ret void
//
// AARCH64-LABEL: define dso_local void @testPrimitiveLongDouble(
// AARCH64-SAME: ptr noundef [[LD:%.*]]) #[[ATTR0]] {
// AARCH64-NEXT:  [[ENTRY:.*:]]
// AARCH64-NEXT:    [[LD_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-NEXT:    store ptr [[LD]], ptr [[LD_ADDR]], align 8
// AARCH64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[LD_ADDR]], align 8
// AARCH64-NEXT:    ret void
//
void testPrimitiveLongDouble(long double *ld) {
  // padding [10, 15] on x86
  __builtin_clear_padding(ld);
}

// CHECK64-LE-LABEL: define dso_local void @testBitInt(
// CHECK64-LE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// CHECK64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// CHECK64-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// CHECK64-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitInt(
// ARM-LE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// ARM-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// ARM-LE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// ARM-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// ARM-LE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitInt(
// ARM-BE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    store i8 0, ptr [[TMP1]], align 8
// ARM-BE-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    store i8 0, ptr [[TMP2]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-BE-NEXT:    store i8 0, ptr [[TMP3]], align 2
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 1
// ARM-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitInt(
// AARCH64-BE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP1]], align 16
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP2]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP3]], align 2
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 1
// AARCH64-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitInt(_BitInt(97) *bi) {
  // Storage is widened to 128 bits; clear bits [97, 128).
  __builtin_clear_padding(bi);
}

// CHECK64-LE-LABEL: define dso_local void @testBitIntByteAligned(
// CHECK64-LE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP1]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitIntByteAligned(
// ARM-LE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    store i8 0, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitIntByteAligned(
// ARM-BE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    store i8 0, ptr [[TMP1]], align 4
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitIntByteAligned(
// AARCH64-BE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP1]], align 4
// AARCH64-BE-NEXT:    ret void
//
void testBitIntByteAligned(_BitInt(24) *bi) {
  // Storage is widened to 32 bits; clear the leading or trailing byte.
  __builtin_clear_padding(bi);
}

// CHECK64-LE-LABEL: define dso_local void @testVolatileBitInt(
// CHECK64-LE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// CHECK64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// CHECK64-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// CHECK64-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testVolatileBitInt(
// ARM-LE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// ARM-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// ARM-LE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// ARM-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// ARM-LE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testVolatileBitInt(
// ARM-BE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    store i8 0, ptr [[TMP1]], align 8
// ARM-BE-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    store i8 0, ptr [[TMP2]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-BE-NEXT:    store i8 0, ptr [[TMP3]], align 2
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 1
// ARM-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testVolatileBitInt(
// AARCH64-BE-SAME: ptr noundef [[BI:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[BI_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[BI]], ptr [[BI_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BI_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP1]], align 16
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP2]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP3]], align 2
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 1
// AARCH64-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testVolatileBitInt(volatile _BitInt(97) *bi) {
  __builtin_clear_padding(bi);
}


// LINUX-LABEL: define dso_local void @testPrimitiveComplexLongDouble(
// LINUX-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] {
// LINUX-NEXT:  [[ENTRY:.*:]]
// LINUX-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
// LINUX-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
// LINUX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// LINUX-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// LINUX-NEXT:    store i8 0, ptr [[TMP1]], align 2
// LINUX-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// LINUX-NEXT:    store i8 0, ptr [[TMP2]], align 1
// LINUX-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// LINUX-NEXT:    store i8 0, ptr [[TMP3]], align 4
// LINUX-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// LINUX-NEXT:    store i8 0, ptr [[TMP4]], align 1
// LINUX-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// LINUX-NEXT:    store i8 0, ptr [[TMP5]], align 2
// LINUX-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// LINUX-NEXT:    store i8 0, ptr [[TMP6]], align 1
// LINUX-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 26
// LINUX-NEXT:    store i8 0, ptr [[TMP7]], align 2
// LINUX-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 27
// LINUX-NEXT:    store i8 0, ptr [[TMP8]], align 1
// LINUX-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 28
// LINUX-NEXT:    store i8 0, ptr [[TMP9]], align 4
// LINUX-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 29
// LINUX-NEXT:    store i8 0, ptr [[TMP10]], align 1
// LINUX-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 30
// LINUX-NEXT:    store i8 0, ptr [[TMP11]], align 2
// LINUX-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 31
// LINUX-NEXT:    store i8 0, ptr [[TMP12]], align 1
// LINUX-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testPrimitiveComplexLongDouble(
// WINDOWS-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// WINDOWS-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testPrimitiveComplexLongDouble(
// ARM-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
// ARM-NEXT:    ret void
//
// AARCH64-LABEL: define dso_local void @testPrimitiveComplexLongDouble(
// AARCH64-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] {
// AARCH64-NEXT:  [[ENTRY:.*:]]
// AARCH64-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
// AARCH64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// AARCH64-NEXT:    ret void
//
void testPrimitiveComplexLongDouble(_Complex long double *c) {
  // padding [10, 15] and [26, 31] on x86
  __builtin_clear_padding(c);
}

union U1 {
  int i;
  char c;
};

// CHECK64-LABEL: define dso_local void @testUnionDifferentLength(
// CHECK64-SAME: ptr noundef [[U:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[U_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[U]], ptr [[U_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[U_ADDR]], align 8
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testUnionDifferentLength(
// ARM-SAME: ptr noundef [[U:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[U_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[U]], ptr [[U_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[U_ADDR]], align 4
// ARM-NEXT:    ret void
//
void testUnionDifferentLength(union U1 *u) {
  // This should not clear the object representation bits of the non-active member.
  __builtin_clear_padding(u);
}

struct S {
  __attribute__((aligned(8))) char c1;
};

union U2 {
  struct S s1;
  char c2;
};

// CHECK64-LABEL: define dso_local void @testUnionTailPaddingOfLongestMember(
// CHECK64-SAME: ptr noundef [[U:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[U_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[U]], ptr [[U_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[U_ADDR]], align 8
// CHECK64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// CHECK64-NEXT:    store i8 0, ptr [[TMP1]], align 1
// CHECK64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// CHECK64-NEXT:    store i8 0, ptr [[TMP2]], align 2
// CHECK64-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// CHECK64-NEXT:    store i8 0, ptr [[TMP3]], align 1
// CHECK64-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// CHECK64-NEXT:    store i8 0, ptr [[TMP4]], align 4
// CHECK64-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// CHECK64-NEXT:    store i8 0, ptr [[TMP5]], align 1
// CHECK64-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// CHECK64-NEXT:    store i8 0, ptr [[TMP6]], align 2
// CHECK64-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// CHECK64-NEXT:    store i8 0, ptr [[TMP7]], align 1
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testUnionTailPaddingOfLongestMember(
// ARM-SAME: ptr noundef [[U:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[U_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[U]], ptr [[U_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[U_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-NEXT:    store i8 0, ptr [[TMP1]], align 1
// ARM-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-NEXT:    store i8 0, ptr [[TMP2]], align 2
// ARM-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-NEXT:    store i8 0, ptr [[TMP3]], align 1
// ARM-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// ARM-NEXT:    store i8 0, ptr [[TMP4]], align 4
// ARM-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// ARM-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-NEXT:    store i8 0, ptr [[TMP6]], align 2
// ARM-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-NEXT:    store i8 0, ptr [[TMP7]], align 1
// ARM-NEXT:    ret void
//
void testUnionTailPaddingOfLongestMember(union U2 *u) {
  // This should clear the tail padding of the longest member.
  // [1 - 7]
  __builtin_clear_padding(u);
}


struct __attribute__((aligned(4))) Foo {
  char a;
  _Alignas(2) char b;
};

struct __attribute__((aligned(4))) Bar {
  char c;
  _Alignas(2) char d;
};

struct __attribute__((aligned(4))) Baz {
  struct Foo foo;
  char e;
  struct Bar bar;
};

// Baz structure:
// "a", PAD_1, "b", PAD_2, "c", PAD_3, PAD_4, PAD_5, "c", PAD_6, "d", PAD_7
// %struct.Baz = type { %struct.Foo, i8, [3 x i8], %struct.Bar }
// %struct.Foo = type { i8, i8, i8, i8 }
// %struct.Bar = type { i8, i8, i8, i8 }

// CHECK64-LABEL: define dso_local void @testStructPaddingInBetweenMembers(
// CHECK64-SAME: ptr noundef [[BAZ:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[BAZ_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[BAZ]], ptr [[BAZ_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BAZ_ADDR]], align 8
// CHECK64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// CHECK64-NEXT:    store i8 0, ptr [[TMP1]], align 1
// CHECK64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// CHECK64-NEXT:    store i8 0, ptr [[TMP2]], align 1
// CHECK64-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// CHECK64-NEXT:    store i8 0, ptr [[TMP3]], align 1
// CHECK64-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// CHECK64-NEXT:    store i8 0, ptr [[TMP4]], align 2
// CHECK64-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// CHECK64-NEXT:    store i8 0, ptr [[TMP5]], align 1
// CHECK64-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// CHECK64-NEXT:    store i8 0, ptr [[TMP6]], align 1
// CHECK64-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// CHECK64-NEXT:    store i8 0, ptr [[TMP7]], align 1
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testStructPaddingInBetweenMembers(
// ARM-SAME: ptr noundef [[BAZ:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[BAZ_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[BAZ]], ptr [[BAZ_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BAZ_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-NEXT:    store i8 0, ptr [[TMP1]], align 1
// ARM-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-NEXT:    store i8 0, ptr [[TMP2]], align 1
// ARM-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// ARM-NEXT:    store i8 0, ptr [[TMP3]], align 1
// ARM-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ARM-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// ARM-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// ARM-NEXT:    store i8 0, ptr [[TMP7]], align 1
// ARM-NEXT:    ret void
//
void testStructPaddingInBetweenMembers(struct Baz *baz) {
  // this should clear all the padding in between various members
  __builtin_clear_padding(baz);
}

// CHECK64-LABEL: define dso_local void @testStructVolatile(
// CHECK64-SAME: ptr noundef [[BAZ:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[BAZ_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[BAZ]], ptr [[BAZ_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BAZ_ADDR]], align 8
// CHECK64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// CHECK64-NEXT:    store i8 0, ptr [[TMP1]], align 1
// CHECK64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// CHECK64-NEXT:    store i8 0, ptr [[TMP2]], align 1
// CHECK64-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// CHECK64-NEXT:    store i8 0, ptr [[TMP3]], align 1
// CHECK64-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// CHECK64-NEXT:    store i8 0, ptr [[TMP4]], align 2
// CHECK64-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// CHECK64-NEXT:    store i8 0, ptr [[TMP5]], align 1
// CHECK64-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// CHECK64-NEXT:    store i8 0, ptr [[TMP6]], align 1
// CHECK64-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// CHECK64-NEXT:    store i8 0, ptr [[TMP7]], align 1
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testStructVolatile(
// ARM-SAME: ptr noundef [[BAZ:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[BAZ_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[BAZ]], ptr [[BAZ_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BAZ_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-NEXT:    store i8 0, ptr [[TMP1]], align 1
// ARM-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-NEXT:    store i8 0, ptr [[TMP2]], align 1
// ARM-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// ARM-NEXT:    store i8 0, ptr [[TMP3]], align 1
// ARM-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ARM-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// ARM-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// ARM-NEXT:    store i8 0, ptr [[TMP7]], align 1
// ARM-NEXT:    ret void
//
void testStructVolatile(volatile struct Baz *baz) {
  // this should clear all the padding in between various members
  __builtin_clear_padding(baz);
}




struct S3 {
  long double l;
  _Bool b;
};

// LINUX-LABEL: define dso_local void @testStructWithLongDouble(
// LINUX-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// LINUX-NEXT:  [[ENTRY:.*:]]
// LINUX-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// LINUX-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// LINUX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// LINUX-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// LINUX-NEXT:    store i8 0, ptr [[TMP1]], align 2
// LINUX-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// LINUX-NEXT:    store i8 0, ptr [[TMP2]], align 1
// LINUX-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// LINUX-NEXT:    store i8 0, ptr [[TMP3]], align 4
// LINUX-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// LINUX-NEXT:    store i8 0, ptr [[TMP4]], align 1
// LINUX-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// LINUX-NEXT:    store i8 0, ptr [[TMP5]], align 2
// LINUX-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// LINUX-NEXT:    store i8 0, ptr [[TMP6]], align 1
// LINUX-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 17
// LINUX-NEXT:    store i8 0, ptr [[TMP7]], align 1
// LINUX-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 18
// LINUX-NEXT:    store i8 0, ptr [[TMP8]], align 2
// LINUX-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 19
// LINUX-NEXT:    store i8 0, ptr [[TMP9]], align 1
// LINUX-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 20
// LINUX-NEXT:    store i8 0, ptr [[TMP10]], align 4
// LINUX-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 21
// LINUX-NEXT:    store i8 0, ptr [[TMP11]], align 1
// LINUX-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 22
// LINUX-NEXT:    store i8 0, ptr [[TMP12]], align 2
// LINUX-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 23
// LINUX-NEXT:    store i8 0, ptr [[TMP13]], align 1
// LINUX-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr [[TMP0]], i32 24
// LINUX-NEXT:    store i8 0, ptr [[TMP14]], align 8
// LINUX-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP0]], i32 25
// LINUX-NEXT:    store i8 0, ptr [[TMP15]], align 1
// LINUX-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 26
// LINUX-NEXT:    store i8 0, ptr [[TMP16]], align 2
// LINUX-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 27
// LINUX-NEXT:    store i8 0, ptr [[TMP17]], align 1
// LINUX-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 28
// LINUX-NEXT:    store i8 0, ptr [[TMP18]], align 4
// LINUX-NEXT:    [[TMP19:%.*]] = getelementptr i8, ptr [[TMP0]], i32 29
// LINUX-NEXT:    store i8 0, ptr [[TMP19]], align 1
// LINUX-NEXT:    [[TMP20:%.*]] = getelementptr i8, ptr [[TMP0]], i32 30
// LINUX-NEXT:    store i8 0, ptr [[TMP20]], align 2
// LINUX-NEXT:    [[TMP21:%.*]] = getelementptr i8, ptr [[TMP0]], i32 31
// LINUX-NEXT:    store i8 0, ptr [[TMP21]], align 1
// LINUX-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testStructWithLongDouble(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// WINDOWS-NEXT:    store i8 0, ptr [[TMP1]], align 1
// WINDOWS-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// WINDOWS-NEXT:    store i8 0, ptr [[TMP2]], align 2
// WINDOWS-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// WINDOWS-NEXT:    store i8 0, ptr [[TMP3]], align 1
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// WINDOWS-NEXT:    store i8 0, ptr [[TMP4]], align 4
// WINDOWS-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// WINDOWS-NEXT:    store i8 0, ptr [[TMP5]], align 1
// WINDOWS-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// WINDOWS-NEXT:    store i8 0, ptr [[TMP6]], align 2
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// WINDOWS-NEXT:    store i8 0, ptr [[TMP7]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testStructWithLongDouble(
// ARM-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// ARM-NEXT:    store i8 0, ptr [[TMP1]], align 1
// ARM-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// ARM-NEXT:    store i8 0, ptr [[TMP2]], align 2
// ARM-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// ARM-NEXT:    store i8 0, ptr [[TMP3]], align 1
// ARM-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// ARM-NEXT:    store i8 0, ptr [[TMP4]], align 4
// ARM-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// ARM-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// ARM-NEXT:    store i8 0, ptr [[TMP6]], align 2
// ARM-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// ARM-NEXT:    store i8 0, ptr [[TMP7]], align 1
// ARM-NEXT:    ret void
//
// AARCH64-LABEL: define dso_local void @testStructWithLongDouble(
// AARCH64-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-NEXT:  [[ENTRY:.*:]]
// AARCH64-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 17
// AARCH64-NEXT:    store i8 0, ptr [[TMP1]], align 1
// AARCH64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 18
// AARCH64-NEXT:    store i8 0, ptr [[TMP2]], align 2
// AARCH64-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 19
// AARCH64-NEXT:    store i8 0, ptr [[TMP3]], align 1
// AARCH64-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 20
// AARCH64-NEXT:    store i8 0, ptr [[TMP4]], align 4
// AARCH64-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 21
// AARCH64-NEXT:    store i8 0, ptr [[TMP5]], align 1
// AARCH64-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 22
// AARCH64-NEXT:    store i8 0, ptr [[TMP6]], align 2
// AARCH64-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 23
// AARCH64-NEXT:    store i8 0, ptr [[TMP7]], align 1
// AARCH64-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 24
// AARCH64-NEXT:    store i8 0, ptr [[TMP8]], align 8
// AARCH64-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 25
// AARCH64-NEXT:    store i8 0, ptr [[TMP9]], align 1
// AARCH64-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 26
// AARCH64-NEXT:    store i8 0, ptr [[TMP10]], align 2
// AARCH64-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 27
// AARCH64-NEXT:    store i8 0, ptr [[TMP11]], align 1
// AARCH64-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 28
// AARCH64-NEXT:    store i8 0, ptr [[TMP12]], align 4
// AARCH64-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 29
// AARCH64-NEXT:    store i8 0, ptr [[TMP13]], align 1
// AARCH64-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr [[TMP0]], i32 30
// AARCH64-NEXT:    store i8 0, ptr [[TMP14]], align 2
// AARCH64-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP0]], i32 31
// AARCH64-NEXT:    store i8 0, ptr [[TMP15]], align 1
// AARCH64-NEXT:    ret void
//
void testStructWithLongDouble(struct S3 *s) {
  // "long double data[0-9]", PAD [10-15], "b", PAD [17-31]
  __builtin_clear_padding(s);
}

struct S11 {
  // will usually occupy 2 bytes:
  unsigned char b1 : 3; // 1st 3 bits (in 1st byte) are b1
  unsigned char b2 : 2; // next 2 bits (in 1st byte). The rest bits in byte 1 are unused
  unsigned char b3 : 6; // 6 bits for b3 - doesn't fit into the 1st byte => starts a 2nd
  unsigned char b4 : 2; // 2 bits for b4 - next (and final) bits in the 2nd byte
};

// CHECK64-LE-LABEL: define dso_local void @testBitFields(
// CHECK64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitFields(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitFields(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -8
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitFields(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -8
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitFields(struct S11 *s) {
  // "b1" [0-2], "b2" [3-4], PAD [5-7], "b3" [8-13], "b4" [14-15]
  // Little endian: preserve byte 0 with 0x1f. Big endian: use 0xf8.
  __builtin_clear_padding(s);
}


struct VolatileBitfield {
  volatile unsigned char a : 5;
  int b : 7;
  volatile int c : 27;
};

// ITANIUM64-LE-LABEL: define dso_local void @testVolatileBitfields(
// ITANIUM64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ITANIUM64-LE-NEXT:  [[ENTRY:.*:]]
// ITANIUM64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// ITANIUM64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ITANIUM64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// ITANIUM64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ITANIUM64-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ITANIUM64-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ITANIUM64-LE-NEXT:    [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
// ITANIUM64-LE-NEXT:    [[TMP8:%.*]] = and i8 [[TMP7]], 7
// ITANIUM64-LE-NEXT:    store i8 [[TMP8]], ptr [[TMP6]], align 1
// ITANIUM64-LE-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testVolatileBitfields(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// WINDOWS-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// WINDOWS-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// WINDOWS-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    store i8 0, ptr [[TMP4]], align 1
// WINDOWS-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP5]], align 2
// WINDOWS-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP6]], align 1
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// WINDOWS-NEXT:    [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
// WINDOWS-NEXT:    [[TMP9:%.*]] = and i8 [[TMP8]], 127
// WINDOWS-NEXT:    store i8 [[TMP9]], ptr [[TMP7]], align 4
// WINDOWS-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// WINDOWS-NEXT:    store i8 0, ptr [[TMP10]], align 1
// WINDOWS-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// WINDOWS-NEXT:    store i8 0, ptr [[TMP11]], align 2
// WINDOWS-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// WINDOWS-NEXT:    store i8 0, ptr [[TMP12]], align 1
// WINDOWS-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// WINDOWS-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP13]], align 1
// WINDOWS-NEXT:    [[TMP15:%.*]] = and i8 [[TMP14]], 7
// WINDOWS-NEXT:    store i8 [[TMP15]], ptr [[TMP13]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testVolatileBitfields(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-LE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ARM-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-LE-NEXT:    [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
// ARM-LE-NEXT:    [[TMP8:%.*]] = and i8 [[TMP7]], 7
// ARM-LE-NEXT:    store i8 [[TMP8]], ptr [[TMP6]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testVolatileBitfields(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -16
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-BE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ARM-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-BE-NEXT:    [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
// ARM-BE-NEXT:    [[TMP8:%.*]] = and i8 [[TMP7]], -32
// ARM-BE-NEXT:    store i8 [[TMP8]], ptr [[TMP6]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testVolatileBitfields(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -16
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// AARCH64-BE-NEXT:    [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
// AARCH64-BE-NEXT:    [[TMP8:%.*]] = and i8 [[TMP7]], -32
// AARCH64-BE-NEXT:    store i8 [[TMP8]], ptr [[TMP6]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testVolatileBitfields(struct VolatileBitfield *s) {
  __builtin_clear_padding(s);
}

// ITANIUM64-LE-LABEL: define dso_local void @testVolatileBitfieldsVolatileStruct(
// ITANIUM64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ITANIUM64-LE-NEXT:  [[ENTRY:.*:]]
// ITANIUM64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// ITANIUM64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ITANIUM64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// ITANIUM64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ITANIUM64-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ITANIUM64-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ITANIUM64-LE-NEXT:    [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
// ITANIUM64-LE-NEXT:    [[TMP8:%.*]] = and i8 [[TMP7]], 7
// ITANIUM64-LE-NEXT:    store i8 [[TMP8]], ptr [[TMP6]], align 1
// ITANIUM64-LE-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testVolatileBitfieldsVolatileStruct(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// WINDOWS-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// WINDOWS-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// WINDOWS-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    store i8 0, ptr [[TMP4]], align 1
// WINDOWS-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP5]], align 2
// WINDOWS-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP6]], align 1
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// WINDOWS-NEXT:    [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
// WINDOWS-NEXT:    [[TMP9:%.*]] = and i8 [[TMP8]], 127
// WINDOWS-NEXT:    store i8 [[TMP9]], ptr [[TMP7]], align 4
// WINDOWS-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// WINDOWS-NEXT:    store i8 0, ptr [[TMP10]], align 1
// WINDOWS-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// WINDOWS-NEXT:    store i8 0, ptr [[TMP11]], align 2
// WINDOWS-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// WINDOWS-NEXT:    store i8 0, ptr [[TMP12]], align 1
// WINDOWS-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// WINDOWS-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP13]], align 1
// WINDOWS-NEXT:    [[TMP15:%.*]] = and i8 [[TMP14]], 7
// WINDOWS-NEXT:    store i8 [[TMP15]], ptr [[TMP13]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testVolatileBitfieldsVolatileStruct(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-LE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ARM-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-LE-NEXT:    [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
// ARM-LE-NEXT:    [[TMP8:%.*]] = and i8 [[TMP7]], 7
// ARM-LE-NEXT:    store i8 [[TMP8]], ptr [[TMP6]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testVolatileBitfieldsVolatileStruct(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -16
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-BE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ARM-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-BE-NEXT:    [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
// ARM-BE-NEXT:    [[TMP8:%.*]] = and i8 [[TMP7]], -32
// ARM-BE-NEXT:    store i8 [[TMP8]], ptr [[TMP6]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testVolatileBitfieldsVolatileStruct(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -16
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// AARCH64-BE-NEXT:    [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
// AARCH64-BE-NEXT:    [[TMP8:%.*]] = and i8 [[TMP7]], -32
// AARCH64-BE-NEXT:    store i8 [[TMP8]], ptr [[TMP6]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testVolatileBitfieldsVolatileStruct(volatile struct VolatileBitfield *s) {
  __builtin_clear_padding(s);
}


// LINUX-LABEL: define dso_local void @testArrayNoPadding(
// LINUX-SAME: ) #[[ATTR0]] {
// LINUX-NEXT:  [[ENTRY:.*:]]
// LINUX-NEXT:    [[I:%.*]] = alloca [4 x i32], align 16
// LINUX-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testArrayNoPadding(
// WINDOWS-SAME: ) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[I:%.*]] = alloca [4 x i32], align 4
// WINDOWS-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testArrayNoPadding(
// ARM-SAME: ) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[I:%.*]] = alloca [4 x i32], align 4
// ARM-NEXT:    ret void
//
// AARCH64-LABEL: define dso_local void @testArrayNoPadding(
// AARCH64-SAME: ) #[[ATTR0]] {
// AARCH64-NEXT:  [[ENTRY:.*:]]
// AARCH64-NEXT:    [[I:%.*]] = alloca [4 x i32], align 4
// AARCH64-NEXT:    ret void
//
void testArrayNoPadding(void) {
  int i[4];
  // there is no padding in the array.
  __builtin_clear_padding(&i);
}

// LINUX-LABEL: define dso_local void @testArrayLongDouble(
// LINUX-SAME: ) #[[ATTR0]] {
// LINUX-NEXT:  [[ENTRY:.*:]]
// LINUX-NEXT:    [[LD:%.*]] = alloca [2 x x86_fp80], align 16
// LINUX-NEXT:    [[TMP0:%.*]] = getelementptr i8, ptr [[LD]], i32 10
// LINUX-NEXT:    store i8 0, ptr [[TMP0]], align 2
// LINUX-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[LD]], i32 11
// LINUX-NEXT:    store i8 0, ptr [[TMP1]], align 1
// LINUX-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[LD]], i32 12
// LINUX-NEXT:    store i8 0, ptr [[TMP2]], align 4
// LINUX-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[LD]], i32 13
// LINUX-NEXT:    store i8 0, ptr [[TMP3]], align 1
// LINUX-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[LD]], i32 14
// LINUX-NEXT:    store i8 0, ptr [[TMP4]], align 2
// LINUX-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[LD]], i32 15
// LINUX-NEXT:    store i8 0, ptr [[TMP5]], align 1
// LINUX-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[LD]], i32 26
// LINUX-NEXT:    store i8 0, ptr [[TMP6]], align 2
// LINUX-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[LD]], i32 27
// LINUX-NEXT:    store i8 0, ptr [[TMP7]], align 1
// LINUX-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[LD]], i32 28
// LINUX-NEXT:    store i8 0, ptr [[TMP8]], align 4
// LINUX-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[LD]], i32 29
// LINUX-NEXT:    store i8 0, ptr [[TMP9]], align 1
// LINUX-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[LD]], i32 30
// LINUX-NEXT:    store i8 0, ptr [[TMP10]], align 2
// LINUX-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[LD]], i32 31
// LINUX-NEXT:    store i8 0, ptr [[TMP11]], align 1
// LINUX-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testArrayLongDouble(
// WINDOWS-SAME: ) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[LD:%.*]] = alloca [2 x double], align 8
// WINDOWS-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testArrayLongDouble(
// ARM-SAME: ) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[LD:%.*]] = alloca [2 x double], align 8
// ARM-NEXT:    ret void
//
// AARCH64-LABEL: define dso_local void @testArrayLongDouble(
// AARCH64-SAME: ) #[[ATTR0]] {
// AARCH64-NEXT:  [[ENTRY:.*:]]
// AARCH64-NEXT:    [[LD:%.*]] = alloca [2 x fp128], align 16
// AARCH64-NEXT:    ret void
//
void testArrayLongDouble() {
  // long double 0, [0-9] PAD [10-15]
  // long double 1, [16-25] PAD [26-31]
  long double ld[2];
  __builtin_clear_padding(&ld);
}

// LINUX-LABEL: define dso_local void @testArrayOfStruct(
// LINUX-SAME: ) #[[ATTR0]] {
// LINUX-NEXT:  [[ENTRY:.*:]]
// LINUX-NEXT:    [[S:%.*]] = alloca [2 x [[STRUCT_S_LOCAL:%.*]]], align 16
// LINUX-NEXT:    [[TMP0:%.*]] = getelementptr i8, ptr [[S]], i32 5
// LINUX-NEXT:    store i8 0, ptr [[TMP0]], align 1
// LINUX-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[S]], i32 6
// LINUX-NEXT:    store i8 0, ptr [[TMP1]], align 2
// LINUX-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[S]], i32 7
// LINUX-NEXT:    store i8 0, ptr [[TMP2]], align 1
// LINUX-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[S]], i32 13
// LINUX-NEXT:    store i8 0, ptr [[TMP3]], align 1
// LINUX-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[S]], i32 14
// LINUX-NEXT:    store i8 0, ptr [[TMP4]], align 2
// LINUX-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[S]], i32 15
// LINUX-NEXT:    store i8 0, ptr [[TMP5]], align 1
// LINUX-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[S]], i32 21
// LINUX-NEXT:    store i8 0, ptr [[TMP6]], align 1
// LINUX-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[S]], i32 22
// LINUX-NEXT:    store i8 0, ptr [[TMP7]], align 2
// LINUX-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[S]], i32 23
// LINUX-NEXT:    store i8 0, ptr [[TMP8]], align 1
// LINUX-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[S]], i32 29
// LINUX-NEXT:    store i8 0, ptr [[TMP9]], align 1
// LINUX-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[S]], i32 30
// LINUX-NEXT:    store i8 0, ptr [[TMP10]], align 2
// LINUX-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[S]], i32 31
// LINUX-NEXT:    store i8 0, ptr [[TMP11]], align 1
// LINUX-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testArrayOfStruct(
// WINDOWS-SAME: ) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S:%.*]] = alloca [2 x [[STRUCT_S_LOCAL:%.*]]], align 4
// WINDOWS-NEXT:    [[TMP0:%.*]] = getelementptr i8, ptr [[S]], i32 5
// WINDOWS-NEXT:    store i8 0, ptr [[TMP0]], align 1
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[S]], i32 6
// WINDOWS-NEXT:    store i8 0, ptr [[TMP1]], align 2
// WINDOWS-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[S]], i32 7
// WINDOWS-NEXT:    store i8 0, ptr [[TMP2]], align 1
// WINDOWS-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[S]], i32 13
// WINDOWS-NEXT:    store i8 0, ptr [[TMP3]], align 1
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[S]], i32 14
// WINDOWS-NEXT:    store i8 0, ptr [[TMP4]], align 2
// WINDOWS-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[S]], i32 15
// WINDOWS-NEXT:    store i8 0, ptr [[TMP5]], align 1
// WINDOWS-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[S]], i32 21
// WINDOWS-NEXT:    store i8 0, ptr [[TMP6]], align 1
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[S]], i32 22
// WINDOWS-NEXT:    store i8 0, ptr [[TMP7]], align 2
// WINDOWS-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[S]], i32 23
// WINDOWS-NEXT:    store i8 0, ptr [[TMP8]], align 1
// WINDOWS-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[S]], i32 29
// WINDOWS-NEXT:    store i8 0, ptr [[TMP9]], align 1
// WINDOWS-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[S]], i32 30
// WINDOWS-NEXT:    store i8 0, ptr [[TMP10]], align 2
// WINDOWS-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[S]], i32 31
// WINDOWS-NEXT:    store i8 0, ptr [[TMP11]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testArrayOfStruct(
// ARM-SAME: ) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[S:%.*]] = alloca [2 x [[STRUCT_S_LOCAL:%.*]]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = getelementptr i8, ptr [[S]], i32 5
// ARM-NEXT:    store i8 0, ptr [[TMP0]], align 1
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[S]], i32 6
// ARM-NEXT:    store i8 0, ptr [[TMP1]], align 2
// ARM-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[S]], i32 7
// ARM-NEXT:    store i8 0, ptr [[TMP2]], align 1
// ARM-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[S]], i32 13
// ARM-NEXT:    store i8 0, ptr [[TMP3]], align 1
// ARM-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[S]], i32 14
// ARM-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ARM-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[S]], i32 15
// ARM-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[S]], i32 21
// ARM-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[S]], i32 22
// ARM-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[S]], i32 23
// ARM-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[S]], i32 29
// ARM-NEXT:    store i8 0, ptr [[TMP9]], align 1
// ARM-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[S]], i32 30
// ARM-NEXT:    store i8 0, ptr [[TMP10]], align 2
// ARM-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[S]], i32 31
// ARM-NEXT:    store i8 0, ptr [[TMP11]], align 1
// ARM-NEXT:    ret void
//
// AARCH64-LABEL: define dso_local void @testArrayOfStruct(
// AARCH64-SAME: ) #[[ATTR0]] {
// AARCH64-NEXT:  [[ENTRY:.*:]]
// AARCH64-NEXT:    [[S:%.*]] = alloca [2 x [[STRUCT_S_LOCAL:%.*]]], align 4
// AARCH64-NEXT:    [[TMP0:%.*]] = getelementptr i8, ptr [[S]], i32 5
// AARCH64-NEXT:    store i8 0, ptr [[TMP0]], align 1
// AARCH64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[S]], i32 6
// AARCH64-NEXT:    store i8 0, ptr [[TMP1]], align 2
// AARCH64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[S]], i32 7
// AARCH64-NEXT:    store i8 0, ptr [[TMP2]], align 1
// AARCH64-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[S]], i32 13
// AARCH64-NEXT:    store i8 0, ptr [[TMP3]], align 1
// AARCH64-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[S]], i32 14
// AARCH64-NEXT:    store i8 0, ptr [[TMP4]], align 2
// AARCH64-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[S]], i32 15
// AARCH64-NEXT:    store i8 0, ptr [[TMP5]], align 1
// AARCH64-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[S]], i32 21
// AARCH64-NEXT:    store i8 0, ptr [[TMP6]], align 1
// AARCH64-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[S]], i32 22
// AARCH64-NEXT:    store i8 0, ptr [[TMP7]], align 2
// AARCH64-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[S]], i32 23
// AARCH64-NEXT:    store i8 0, ptr [[TMP8]], align 1
// AARCH64-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[S]], i32 29
// AARCH64-NEXT:    store i8 0, ptr [[TMP9]], align 1
// AARCH64-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[S]], i32 30
// AARCH64-NEXT:    store i8 0, ptr [[TMP10]], align 2
// AARCH64-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[S]], i32 31
// AARCH64-NEXT:    store i8 0, ptr [[TMP11]], align 1
// AARCH64-NEXT:    ret void
//
void testArrayOfStruct(void) {
  struct S_local {
    int i1;
    char c1;
    int i2;
    char c2;
  };

  // S[0].i1 [0-3], S[0].c1 [4], PAD [5-7],
  // S[0].i2 [8-11], S[0].c2 [12], PAD [13-15],
  // S[1].i1 [16-19], S[1].c1 [20], PAD [21-23],
  // S[1].i2 [24-27], S[1].c2 [28], PAD [29-31]

  struct S_local s[2];
  __builtin_clear_padding(&s);
}

struct ArrOfStructsWithPadding {
  struct Bar bars[2];
};

// ArrOfStructsWithPadding structure:
// "c" (1), PAD_1, "d" (1), PAD_2, "c" (2), PAD_3, "d" (2), PAD_4
// %struct.ArrOfStructsWithPadding = type { [2 x %struct.Bar] }

// CHECK64-LABEL: define dso_local void @testArrOfStructsWithPadding(
// CHECK64-SAME: ptr noundef [[ARR:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[ARR_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[ARR]], ptr [[ARR_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8
// CHECK64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// CHECK64-NEXT:    store i8 0, ptr [[TMP1]], align 1
// CHECK64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// CHECK64-NEXT:    store i8 0, ptr [[TMP2]], align 1
// CHECK64-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// CHECK64-NEXT:    store i8 0, ptr [[TMP3]], align 1
// CHECK64-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// CHECK64-NEXT:    store i8 0, ptr [[TMP4]], align 1
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testArrOfStructsWithPadding(
// ARM-SAME: ptr noundef [[ARR:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[ARR_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[ARR]], ptr [[ARR_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-NEXT:    store i8 0, ptr [[TMP1]], align 1
// ARM-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-NEXT:    store i8 0, ptr [[TMP2]], align 1
// ARM-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// ARM-NEXT:    store i8 0, ptr [[TMP3]], align 1
// ARM-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-NEXT:    ret void
//
void testArrOfStructsWithPadding(struct ArrOfStructsWithPadding *arr) {
  __builtin_clear_padding(arr);
}

// CHECK64-LABEL: define dso_local void @testAtomic(
// CHECK64-SAME: ptr noundef [[BAR:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[BAR_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[BAR]], ptr [[BAR_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BAR_ADDR]], align 8
// CHECK64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// CHECK64-NEXT:    store i8 0, ptr [[TMP1]], align 1
// CHECK64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// CHECK64-NEXT:    store i8 0, ptr [[TMP2]], align 1
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testAtomic(
// ARM-SAME: ptr noundef [[BAR:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[BAR_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[BAR]], ptr [[BAR_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BAR_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-NEXT:    store i8 0, ptr [[TMP1]], align 1
// ARM-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-NEXT:    store i8 0, ptr [[TMP2]], align 1
// ARM-NEXT:    ret void
//
void testAtomic(_Atomic(struct Bar)* bar) {
  __builtin_clear_padding(bar);
}

typedef float Float3Vec __attribute__((ext_vector_type(3)));
typedef long double LongDouble3Vec __attribute__((ext_vector_type(3)));

// CHECK64-LABEL: define dso_local void @testAttributedType(
// CHECK64-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// CHECK64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// CHECK64-NEXT:    store i8 0, ptr [[TMP1]], align 4
// CHECK64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// CHECK64-NEXT:    store i8 0, ptr [[TMP2]], align 1
// CHECK64-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// CHECK64-NEXT:    store i8 0, ptr [[TMP3]], align 2
// CHECK64-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// CHECK64-NEXT:    store i8 0, ptr [[TMP4]], align 1
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testAttributedType(
// ARM-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// ARM-NEXT:    store i8 0, ptr [[TMP1]], align 4
// ARM-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// ARM-NEXT:    store i8 0, ptr [[TMP2]], align 1
// ARM-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// ARM-NEXT:    store i8 0, ptr [[TMP3]], align 2
// ARM-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// ARM-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-NEXT:    ret void
//
void testAttributedType(Float3Vec* v) {
  __builtin_clear_padding(v);
}

// LINUX-LABEL: define dso_local void @testAttributedLongDoubleType(
// LINUX-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// LINUX-NEXT:  [[ENTRY:.*:]]
// LINUX-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
// LINUX-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
// LINUX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// LINUX-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 30
// LINUX-NEXT:    store i8 0, ptr [[TMP1]], align 2
// LINUX-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 31
// LINUX-NEXT:    store i8 0, ptr [[TMP2]], align 1
// LINUX-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 32
// LINUX-NEXT:    store i8 0, ptr [[TMP3]], align 32
// LINUX-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 33
// LINUX-NEXT:    store i8 0, ptr [[TMP4]], align 1
// LINUX-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 34
// LINUX-NEXT:    store i8 0, ptr [[TMP5]], align 2
// LINUX-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 35
// LINUX-NEXT:    store i8 0, ptr [[TMP6]], align 1
// LINUX-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 36
// LINUX-NEXT:    store i8 0, ptr [[TMP7]], align 4
// LINUX-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 37
// LINUX-NEXT:    store i8 0, ptr [[TMP8]], align 1
// LINUX-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 38
// LINUX-NEXT:    store i8 0, ptr [[TMP9]], align 2
// LINUX-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 39
// LINUX-NEXT:    store i8 0, ptr [[TMP10]], align 1
// LINUX-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 40
// LINUX-NEXT:    store i8 0, ptr [[TMP11]], align 8
// LINUX-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 41
// LINUX-NEXT:    store i8 0, ptr [[TMP12]], align 1
// LINUX-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 42
// LINUX-NEXT:    store i8 0, ptr [[TMP13]], align 2
// LINUX-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr [[TMP0]], i32 43
// LINUX-NEXT:    store i8 0, ptr [[TMP14]], align 1
// LINUX-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP0]], i32 44
// LINUX-NEXT:    store i8 0, ptr [[TMP15]], align 4
// LINUX-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 45
// LINUX-NEXT:    store i8 0, ptr [[TMP16]], align 1
// LINUX-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 46
// LINUX-NEXT:    store i8 0, ptr [[TMP17]], align 2
// LINUX-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 47
// LINUX-NEXT:    store i8 0, ptr [[TMP18]], align 1
// LINUX-NEXT:    [[TMP19:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48
// LINUX-NEXT:    store i8 0, ptr [[TMP19]], align 16
// LINUX-NEXT:    [[TMP20:%.*]] = getelementptr i8, ptr [[TMP0]], i32 49
// LINUX-NEXT:    store i8 0, ptr [[TMP20]], align 1
// LINUX-NEXT:    [[TMP21:%.*]] = getelementptr i8, ptr [[TMP0]], i32 50
// LINUX-NEXT:    store i8 0, ptr [[TMP21]], align 2
// LINUX-NEXT:    [[TMP22:%.*]] = getelementptr i8, ptr [[TMP0]], i32 51
// LINUX-NEXT:    store i8 0, ptr [[TMP22]], align 1
// LINUX-NEXT:    [[TMP23:%.*]] = getelementptr i8, ptr [[TMP0]], i32 52
// LINUX-NEXT:    store i8 0, ptr [[TMP23]], align 4
// LINUX-NEXT:    [[TMP24:%.*]] = getelementptr i8, ptr [[TMP0]], i32 53
// LINUX-NEXT:    store i8 0, ptr [[TMP24]], align 1
// LINUX-NEXT:    [[TMP25:%.*]] = getelementptr i8, ptr [[TMP0]], i32 54
// LINUX-NEXT:    store i8 0, ptr [[TMP25]], align 2
// LINUX-NEXT:    [[TMP26:%.*]] = getelementptr i8, ptr [[TMP0]], i32 55
// LINUX-NEXT:    store i8 0, ptr [[TMP26]], align 1
// LINUX-NEXT:    [[TMP27:%.*]] = getelementptr i8, ptr [[TMP0]], i32 56
// LINUX-NEXT:    store i8 0, ptr [[TMP27]], align 8
// LINUX-NEXT:    [[TMP28:%.*]] = getelementptr i8, ptr [[TMP0]], i32 57
// LINUX-NEXT:    store i8 0, ptr [[TMP28]], align 1
// LINUX-NEXT:    [[TMP29:%.*]] = getelementptr i8, ptr [[TMP0]], i32 58
// LINUX-NEXT:    store i8 0, ptr [[TMP29]], align 2
// LINUX-NEXT:    [[TMP30:%.*]] = getelementptr i8, ptr [[TMP0]], i32 59
// LINUX-NEXT:    store i8 0, ptr [[TMP30]], align 1
// LINUX-NEXT:    [[TMP31:%.*]] = getelementptr i8, ptr [[TMP0]], i32 60
// LINUX-NEXT:    store i8 0, ptr [[TMP31]], align 4
// LINUX-NEXT:    [[TMP32:%.*]] = getelementptr i8, ptr [[TMP0]], i32 61
// LINUX-NEXT:    store i8 0, ptr [[TMP32]], align 1
// LINUX-NEXT:    [[TMP33:%.*]] = getelementptr i8, ptr [[TMP0]], i32 62
// LINUX-NEXT:    store i8 0, ptr [[TMP33]], align 2
// LINUX-NEXT:    [[TMP34:%.*]] = getelementptr i8, ptr [[TMP0]], i32 63
// LINUX-NEXT:    store i8 0, ptr [[TMP34]], align 1
// LINUX-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testAttributedLongDoubleType(
// WINDOWS-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 24
// WINDOWS-NEXT:    store i8 0, ptr [[TMP1]], align 8
// WINDOWS-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 25
// WINDOWS-NEXT:    store i8 0, ptr [[TMP2]], align 1
// WINDOWS-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 26
// WINDOWS-NEXT:    store i8 0, ptr [[TMP3]], align 2
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 27
// WINDOWS-NEXT:    store i8 0, ptr [[TMP4]], align 1
// WINDOWS-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 28
// WINDOWS-NEXT:    store i8 0, ptr [[TMP5]], align 4
// WINDOWS-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 29
// WINDOWS-NEXT:    store i8 0, ptr [[TMP6]], align 1
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 30
// WINDOWS-NEXT:    store i8 0, ptr [[TMP7]], align 2
// WINDOWS-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 31
// WINDOWS-NEXT:    store i8 0, ptr [[TMP8]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testAttributedLongDoubleType(
// ARM-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 24
// ARM-NEXT:    store i8 0, ptr [[TMP1]], align 8
// ARM-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 25
// ARM-NEXT:    store i8 0, ptr [[TMP2]], align 1
// ARM-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 26
// ARM-NEXT:    store i8 0, ptr [[TMP3]], align 2
// ARM-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 27
// ARM-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 28
// ARM-NEXT:    store i8 0, ptr [[TMP5]], align 4
// ARM-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 29
// ARM-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 30
// ARM-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 31
// ARM-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-NEXT:    ret void
//
// AARCH64-LABEL: define dso_local void @testAttributedLongDoubleType(
// AARCH64-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// AARCH64-NEXT:  [[ENTRY:.*:]]
// AARCH64-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
// AARCH64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// AARCH64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 48
// AARCH64-NEXT:    store i8 0, ptr [[TMP1]], align 16
// AARCH64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 49
// AARCH64-NEXT:    store i8 0, ptr [[TMP2]], align 1
// AARCH64-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 50
// AARCH64-NEXT:    store i8 0, ptr [[TMP3]], align 2
// AARCH64-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 51
// AARCH64-NEXT:    store i8 0, ptr [[TMP4]], align 1
// AARCH64-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 52
// AARCH64-NEXT:    store i8 0, ptr [[TMP5]], align 4
// AARCH64-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 53
// AARCH64-NEXT:    store i8 0, ptr [[TMP6]], align 1
// AARCH64-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 54
// AARCH64-NEXT:    store i8 0, ptr [[TMP7]], align 2
// AARCH64-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 55
// AARCH64-NEXT:    store i8 0, ptr [[TMP8]], align 1
// AARCH64-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 56
// AARCH64-NEXT:    store i8 0, ptr [[TMP9]], align 8
// AARCH64-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 57
// AARCH64-NEXT:    store i8 0, ptr [[TMP10]], align 1
// AARCH64-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 58
// AARCH64-NEXT:    store i8 0, ptr [[TMP11]], align 2
// AARCH64-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 59
// AARCH64-NEXT:    store i8 0, ptr [[TMP12]], align 1
// AARCH64-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 60
// AARCH64-NEXT:    store i8 0, ptr [[TMP13]], align 4
// AARCH64-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr [[TMP0]], i32 61
// AARCH64-NEXT:    store i8 0, ptr [[TMP14]], align 1
// AARCH64-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP0]], i32 62
// AARCH64-NEXT:    store i8 0, ptr [[TMP15]], align 2
// AARCH64-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 63
// AARCH64-NEXT:    store i8 0, ptr [[TMP16]], align 1
// AARCH64-NEXT:    ret void
//
void testAttributedLongDoubleType(LongDouble3Vec *v) {
  // long double elements occupy [0-9], [16-25], [32-41] on x86.
  __builtin_clear_padding(v);
}

struct UnnamedBitfieldSingleBit {
  unsigned char a : 3;
  unsigned char   : 1;
  unsigned char b : 4;
};

// CHECK64-LE-LABEL: define dso_local void @testUnnamedBitfieldSingleBit(
// CHECK64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -9
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testUnnamedBitfieldSingleBit(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -9
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testUnnamedBitfieldSingleBit(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -17
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testUnnamedBitfieldSingleBit(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -17
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testUnnamedBitfieldSingleBit(struct UnnamedBitfieldSingleBit *s) {
  // Little endian: a[bits 0-2], unnamed[bit 3], b[bits 4-7].
  // Clear bit 3 on little endian, or bit 4 on big endian.
  // Mask: 0b11110111 == -9
  __builtin_clear_padding(s);
}

struct UnnamedBitfieldMiddle {
  unsigned char a : 3;
  unsigned char   : 2;
  unsigned char b : 3;
};

// CHECK64-LABEL: define dso_local void @testUnnamedBitfieldMiddle(
// CHECK64-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// CHECK64-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -25
// CHECK64-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testUnnamedBitfieldMiddle(
// ARM-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -25
// ARM-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-NEXT:    ret void
//
void testUnnamedBitfieldMiddle(struct UnnamedBitfieldMiddle *s) {
  // byte 0: a[0-2], unnamed[3-4], b[5-7]
  // bits 3-4 must be cleared
  // Mask: 0b11100111 == -25
  __builtin_clear_padding(s);
}

struct UnnamedBitfieldSurrounding {
  unsigned char   : 2;
  unsigned char a : 4;
  unsigned char   : 2;
};

// CHECK64-LABEL: define dso_local void @testUnnamedBitfieldSurrounding(
// CHECK64-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// CHECK64-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -4
// CHECK64-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// CHECK64-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// CHECK64-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 63
// CHECK64-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testUnnamedBitfieldSurrounding(
// ARM-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -4
// ARM-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 63
// ARM-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-NEXT:    ret void
//
void testUnnamedBitfieldSurrounding(struct UnnamedBitfieldSurrounding *s) {
  // byte 0: unnamed[0-1], a[2-5], unnamed[6-7]
  // bits 0-1 and 6-7 must be cleared
  // Masks:
  //   0b11111100 == -4
  //   0b00111111 == 63
  __builtin_clear_padding(s);
}

struct UnnamedZeroWidthBitfield {
  unsigned char a : 4;
  unsigned int  : 0;
  unsigned int b : 4;
};

// CHECK64-LE-LABEL: define dso_local void @testUnnamedZeroWidthBitfield(
// CHECK64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// CHECK64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// CHECK64-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// CHECK64-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// CHECK64-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// CHECK64-LE-NEXT:    [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
// CHECK64-LE-NEXT:    [[TMP9:%.*]] = and i8 [[TMP8]], 15
// CHECK64-LE-NEXT:    store i8 [[TMP9]], ptr [[TMP7]], align 4
// CHECK64-LE-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP10]], align 1
// CHECK64-LE-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP11]], align 2
// CHECK64-LE-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP12]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testUnnamedZeroWidthBitfield(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-LE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// ARM-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// ARM-LE-NEXT:    [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
// ARM-LE-NEXT:    [[TMP9:%.*]] = and i8 [[TMP8]], 15
// ARM-LE-NEXT:    store i8 [[TMP9]], ptr [[TMP7]], align 4
// ARM-LE-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// ARM-LE-NEXT:    store i8 0, ptr [[TMP10]], align 1
// ARM-LE-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-LE-NEXT:    store i8 0, ptr [[TMP11]], align 2
// ARM-LE-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-LE-NEXT:    store i8 0, ptr [[TMP12]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testUnnamedZeroWidthBitfield(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -16
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-BE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// ARM-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// ARM-BE-NEXT:    [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
// ARM-BE-NEXT:    [[TMP9:%.*]] = and i8 [[TMP8]], -16
// ARM-BE-NEXT:    store i8 [[TMP9]], ptr [[TMP7]], align 4
// ARM-BE-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// ARM-BE-NEXT:    store i8 0, ptr [[TMP10]], align 1
// ARM-BE-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-BE-NEXT:    store i8 0, ptr [[TMP11]], align 2
// ARM-BE-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-BE-NEXT:    store i8 0, ptr [[TMP12]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testUnnamedZeroWidthBitfield(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -16
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// AARCH64-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// AARCH64-BE-NEXT:    [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
// AARCH64-BE-NEXT:    [[TMP9:%.*]] = and i8 [[TMP8]], -16
// AARCH64-BE-NEXT:    store i8 [[TMP9]], ptr [[TMP7]], align 4
// AARCH64-BE-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP10]], align 1
// AARCH64-BE-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP11]], align 2
// AARCH64-BE-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP12]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testUnnamedZeroWidthBitfield(struct UnnamedZeroWidthBitfield *s) {
  // The masks below describe little endian; big endian uses 0xf0.
  // byte 0: a[0-3], unnamed[4-7]
  // bytes 1-3: struct padding
  // bytes 4-7: b[bits 0-3], tail padding[bits 4-31]
  //
  // byte 0:   clear bits 4-7
  //           mask: 0b00001111 == 15
  //
  // byte 1-3: clear all bits
  //           3 x store i8 0
  //
  // byte 4-7: clear bits 4-31
  //           mask: 0b00001111 == 15
  //           3 x store i8 0
  __builtin_clear_padding(s);
}

struct UnnamedBitfieldMultiByte {
  unsigned short a : 4;
  unsigned short   : 8;
  unsigned short b : 4;
};

// CHECK64-LE-LABEL: define dso_local void @testUnnamedBitfieldMultiByte(
// CHECK64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// CHECK64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// CHECK64-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// CHECK64-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -16
// CHECK64-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testUnnamedBitfieldMultiByte(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -16
// ARM-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testUnnamedBitfieldMultiByte(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -16
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 15
// ARM-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testUnnamedBitfieldMultiByte(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -16
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 15
// AARCH64-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testUnnamedBitfieldMultiByte(struct UnnamedBitfieldMultiByte *s) {
  // The masks below describe little endian; big endian swaps them.
  // 2 bytes: a[0-3], unnamed[4-11], b[12-15]
  // byte 0: clear bits 4-7
  // byte 1: clear bits 0-3
  //
  // Masks:
  //   0b00001111 ==  15
  //   0b11110000 == -16
  __builtin_clear_padding(s);
}

// Complete bytes require no clearing, including a full 64-bit bitfield.
struct BitfieldFullBytes {
  unsigned char first : 8;
  unsigned char second : 8;
  unsigned short half : 16;
  unsigned int word : 32;
  unsigned long long wide : 64;
};

// CHECK64-LABEL: define dso_local void @testBitfieldFullBytes(
// CHECK64-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testBitfieldFullBytes(
// ARM-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-NEXT:    ret void
//
void testBitfieldFullBytes(struct BitfieldFullBytes *s) {
  __builtin_clear_padding(s);
}

// The value ends exactly at a byte boundary. Preserve masks are 0xf8, 0xff
// on little endian and 0x1f, 0xff on big endian.
struct BitfieldEndAligned {
  unsigned short : 3;
  unsigned short value : 13;
};

// CHECK64-LE-LABEL: define dso_local void @testBitfieldEndAligned(
// CHECK64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -8
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldEndAligned(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -8
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldEndAligned(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldEndAligned(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldEndAligned(struct BitfieldEndAligned *s) {
  __builtin_clear_padding(s);
}

// A normal field with two partial endpoints and a complete middle byte.
// Preserve masks are 0xf8, 0xff, 0x1f, 0x00 on little endian and
// 0x1f, 0xff, 0xf8, 0x00 on big endian.
struct BitfieldPartialEnds {
  unsigned int : 3;
  unsigned int value : 18;
  unsigned int : 11;
};

// CHECK64-LE-LABEL: define dso_local void @testBitfieldPartialEnds(
// CHECK64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -8
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// CHECK64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// CHECK64-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 2
// CHECK64-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 31
// CHECK64-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 2
// CHECK64-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP7]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldPartialEnds(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -8
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 2
// ARM-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 31
// ARM-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 2
// ARM-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    store i8 0, ptr [[TMP7]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldPartialEnds(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 2
// ARM-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -8
// ARM-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 2
// ARM-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    store i8 0, ptr [[TMP7]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldPartialEnds(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 2
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -8
// AARCH64-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 2
// AARCH64-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP7]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldPartialEnds(struct BitfieldPartialEnds *s) {
  __builtin_clear_padding(s);
}

// An asymmetric single-bit interval catches endpoint and reflection errors.
struct BitfieldSingleValueBit {
  unsigned char : 2;
  unsigned char value : 1;
  unsigned char : 5;
};

// CHECK64-LE-LABEL: define dso_local void @testBitfieldSingleValueBit(
// CHECK64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -4
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// CHECK64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// CHECK64-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 7
// CHECK64-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldSingleValueBit(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -4
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 7
// ARM-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldSingleValueBit(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -32
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 63
// ARM-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldSingleValueBit(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -32
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 63
// AARCH64-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldSingleValueBit(struct BitfieldSingleValueBit *s) {
  __builtin_clear_padding(s);
}

// Ordinary members share bitfield containers on Arm, and separate two runs of
// bitfields. Clearing padding must preserve every ordinary member.
struct BitfieldMixedMembers {
  unsigned char prefix;
  unsigned int first : 3;
  unsigned char separator;
  unsigned int second : 5;
  unsigned short suffix;
};

// ITANIUM64-LE-LABEL: define dso_local void @testBitfieldMixedMembers(
// ITANIUM64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ITANIUM64-LE-NEXT:  [[ENTRY:.*:]]
// ITANIUM64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// ITANIUM64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ITANIUM64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 7
// ITANIUM64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ITANIUM64-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ITANIUM64-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 31
// ITANIUM64-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ITANIUM64-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ITANIUM64-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ITANIUM64-LE-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testBitfieldMixedMembers(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    store i8 0, ptr [[TMP1]], align 1
// WINDOWS-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP2]], align 2
// WINDOWS-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP3]], align 1
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// WINDOWS-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 4
// WINDOWS-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 7
// WINDOWS-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 4
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// WINDOWS-NEXT:    store i8 0, ptr [[TMP7]], align 1
// WINDOWS-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// WINDOWS-NEXT:    store i8 0, ptr [[TMP8]], align 2
// WINDOWS-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// WINDOWS-NEXT:    store i8 0, ptr [[TMP9]], align 1
// WINDOWS-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// WINDOWS-NEXT:    store i8 0, ptr [[TMP10]], align 1
// WINDOWS-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// WINDOWS-NEXT:    store i8 0, ptr [[TMP11]], align 2
// WINDOWS-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// WINDOWS-NEXT:    store i8 0, ptr [[TMP12]], align 1
// WINDOWS-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// WINDOWS-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP13]], align 4
// WINDOWS-NEXT:    [[TMP15:%.*]] = and i8 [[TMP14]], 31
// WINDOWS-NEXT:    store i8 [[TMP15]], ptr [[TMP13]], align 4
// WINDOWS-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// WINDOWS-NEXT:    store i8 0, ptr [[TMP16]], align 1
// WINDOWS-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// WINDOWS-NEXT:    store i8 0, ptr [[TMP17]], align 2
// WINDOWS-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// WINDOWS-NEXT:    store i8 0, ptr [[TMP18]], align 1
// WINDOWS-NEXT:    [[TMP19:%.*]] = getelementptr i8, ptr [[TMP0]], i32 18
// WINDOWS-NEXT:    store i8 0, ptr [[TMP19]], align 2
// WINDOWS-NEXT:    [[TMP20:%.*]] = getelementptr i8, ptr [[TMP0]], i32 19
// WINDOWS-NEXT:    store i8 0, ptr [[TMP20]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldMixedMembers(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 7
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 31
// ARM-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-LE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-LE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldMixedMembers(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -32
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -8
// ARM-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-BE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-BE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldMixedMembers(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -32
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -8
// AARCH64-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// AARCH64-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldMixedMembers(struct BitfieldMixedMembers *s) {
  __builtin_clear_padding(s);
}

// ITANIUM64-LE-LABEL: define dso_local void @testBitfieldMixedMembersVolatileObject(
// ITANIUM64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ITANIUM64-LE-NEXT:  [[ENTRY:.*:]]
// ITANIUM64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// ITANIUM64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ITANIUM64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 7
// ITANIUM64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ITANIUM64-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ITANIUM64-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 31
// ITANIUM64-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ITANIUM64-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ITANIUM64-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ITANIUM64-LE-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testBitfieldMixedMembersVolatileObject(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    store i8 0, ptr [[TMP1]], align 1
// WINDOWS-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP2]], align 2
// WINDOWS-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP3]], align 1
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// WINDOWS-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 4
// WINDOWS-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 7
// WINDOWS-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 4
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// WINDOWS-NEXT:    store i8 0, ptr [[TMP7]], align 1
// WINDOWS-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// WINDOWS-NEXT:    store i8 0, ptr [[TMP8]], align 2
// WINDOWS-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// WINDOWS-NEXT:    store i8 0, ptr [[TMP9]], align 1
// WINDOWS-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// WINDOWS-NEXT:    store i8 0, ptr [[TMP10]], align 1
// WINDOWS-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// WINDOWS-NEXT:    store i8 0, ptr [[TMP11]], align 2
// WINDOWS-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// WINDOWS-NEXT:    store i8 0, ptr [[TMP12]], align 1
// WINDOWS-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// WINDOWS-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP13]], align 4
// WINDOWS-NEXT:    [[TMP15:%.*]] = and i8 [[TMP14]], 31
// WINDOWS-NEXT:    store i8 [[TMP15]], ptr [[TMP13]], align 4
// WINDOWS-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// WINDOWS-NEXT:    store i8 0, ptr [[TMP16]], align 1
// WINDOWS-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// WINDOWS-NEXT:    store i8 0, ptr [[TMP17]], align 2
// WINDOWS-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// WINDOWS-NEXT:    store i8 0, ptr [[TMP18]], align 1
// WINDOWS-NEXT:    [[TMP19:%.*]] = getelementptr i8, ptr [[TMP0]], i32 18
// WINDOWS-NEXT:    store i8 0, ptr [[TMP19]], align 2
// WINDOWS-NEXT:    [[TMP20:%.*]] = getelementptr i8, ptr [[TMP0]], i32 19
// WINDOWS-NEXT:    store i8 0, ptr [[TMP20]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldMixedMembersVolatileObject(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 7
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 31
// ARM-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-LE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-LE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldMixedMembersVolatileObject(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -32
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -8
// ARM-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-BE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-BE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldMixedMembersVolatileObject(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -32
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -8
// AARCH64-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// AARCH64-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldMixedMembersVolatileObject(
    volatile struct BitfieldMixedMembers *s) {
  __builtin_clear_padding(s);
}

struct BitfieldMixedVolatileMembers {
  unsigned char prefix;
  volatile unsigned int first : 3;
  unsigned char separator;
  volatile unsigned int second : 5;
  unsigned short suffix;
};

// ITANIUM64-LE-LABEL: define dso_local void @testBitfieldMixedVolatileMembers(
// ITANIUM64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ITANIUM64-LE-NEXT:  [[ENTRY:.*:]]
// ITANIUM64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// ITANIUM64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ITANIUM64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 7
// ITANIUM64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ITANIUM64-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ITANIUM64-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 31
// ITANIUM64-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ITANIUM64-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ITANIUM64-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ITANIUM64-LE-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testBitfieldMixedVolatileMembers(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    store i8 0, ptr [[TMP1]], align 1
// WINDOWS-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP2]], align 2
// WINDOWS-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP3]], align 1
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// WINDOWS-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 4
// WINDOWS-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 7
// WINDOWS-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 4
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// WINDOWS-NEXT:    store i8 0, ptr [[TMP7]], align 1
// WINDOWS-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// WINDOWS-NEXT:    store i8 0, ptr [[TMP8]], align 2
// WINDOWS-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// WINDOWS-NEXT:    store i8 0, ptr [[TMP9]], align 1
// WINDOWS-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// WINDOWS-NEXT:    store i8 0, ptr [[TMP10]], align 1
// WINDOWS-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// WINDOWS-NEXT:    store i8 0, ptr [[TMP11]], align 2
// WINDOWS-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// WINDOWS-NEXT:    store i8 0, ptr [[TMP12]], align 1
// WINDOWS-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// WINDOWS-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP13]], align 4
// WINDOWS-NEXT:    [[TMP15:%.*]] = and i8 [[TMP14]], 31
// WINDOWS-NEXT:    store i8 [[TMP15]], ptr [[TMP13]], align 4
// WINDOWS-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// WINDOWS-NEXT:    store i8 0, ptr [[TMP16]], align 1
// WINDOWS-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// WINDOWS-NEXT:    store i8 0, ptr [[TMP17]], align 2
// WINDOWS-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// WINDOWS-NEXT:    store i8 0, ptr [[TMP18]], align 1
// WINDOWS-NEXT:    [[TMP19:%.*]] = getelementptr i8, ptr [[TMP0]], i32 18
// WINDOWS-NEXT:    store i8 0, ptr [[TMP19]], align 2
// WINDOWS-NEXT:    [[TMP20:%.*]] = getelementptr i8, ptr [[TMP0]], i32 19
// WINDOWS-NEXT:    store i8 0, ptr [[TMP20]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldMixedVolatileMembers(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 7
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 31
// ARM-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-LE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-LE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldMixedVolatileMembers(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -32
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -8
// ARM-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-BE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-BE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldMixedVolatileMembers(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -32
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -8
// AARCH64-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// AARCH64-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldMixedVolatileMembers(struct BitfieldMixedVolatileMembers *s) {
  __builtin_clear_padding(s);
}

// ITANIUM64-LE-LABEL: define dso_local void @testBitfieldMixedVolatileMembersAndObject(
// ITANIUM64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ITANIUM64-LE-NEXT:  [[ENTRY:.*:]]
// ITANIUM64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// ITANIUM64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ITANIUM64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 7
// ITANIUM64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ITANIUM64-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ITANIUM64-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 31
// ITANIUM64-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ITANIUM64-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ITANIUM64-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ITANIUM64-LE-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testBitfieldMixedVolatileMembersAndObject(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    store i8 0, ptr [[TMP1]], align 1
// WINDOWS-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP2]], align 2
// WINDOWS-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP3]], align 1
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// WINDOWS-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 4
// WINDOWS-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 7
// WINDOWS-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 4
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// WINDOWS-NEXT:    store i8 0, ptr [[TMP7]], align 1
// WINDOWS-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// WINDOWS-NEXT:    store i8 0, ptr [[TMP8]], align 2
// WINDOWS-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// WINDOWS-NEXT:    store i8 0, ptr [[TMP9]], align 1
// WINDOWS-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// WINDOWS-NEXT:    store i8 0, ptr [[TMP10]], align 1
// WINDOWS-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// WINDOWS-NEXT:    store i8 0, ptr [[TMP11]], align 2
// WINDOWS-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// WINDOWS-NEXT:    store i8 0, ptr [[TMP12]], align 1
// WINDOWS-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// WINDOWS-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP13]], align 4
// WINDOWS-NEXT:    [[TMP15:%.*]] = and i8 [[TMP14]], 31
// WINDOWS-NEXT:    store i8 [[TMP15]], ptr [[TMP13]], align 4
// WINDOWS-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// WINDOWS-NEXT:    store i8 0, ptr [[TMP16]], align 1
// WINDOWS-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// WINDOWS-NEXT:    store i8 0, ptr [[TMP17]], align 2
// WINDOWS-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// WINDOWS-NEXT:    store i8 0, ptr [[TMP18]], align 1
// WINDOWS-NEXT:    [[TMP19:%.*]] = getelementptr i8, ptr [[TMP0]], i32 18
// WINDOWS-NEXT:    store i8 0, ptr [[TMP19]], align 2
// WINDOWS-NEXT:    [[TMP20:%.*]] = getelementptr i8, ptr [[TMP0]], i32 19
// WINDOWS-NEXT:    store i8 0, ptr [[TMP20]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldMixedVolatileMembersAndObject(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 7
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], 31
// ARM-LE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-LE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-LE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldMixedVolatileMembersAndObject(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -32
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -8
// ARM-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-BE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-BE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldMixedVolatileMembersAndObject(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -32
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = and i8 [[TMP5]], -8
// AARCH64-BE-NEXT:    store i8 [[TMP6]], ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP7]], align 2
// AARCH64-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldMixedVolatileMembersAndObject(
    volatile struct BitfieldMixedVolatileMembers *s) {
  __builtin_clear_padding(s);
}

// Both array elements have partial-byte padding, and neither starts at offset
// zero in the enclosing object. Preserve the prefix and suffix too.
struct BitfieldNestedArray {
  unsigned char prefix[3];
  struct BitfieldPartialEnds elements[2];
  unsigned char suffix;
};

// CHECK64-LE-LABEL: define dso_local void @testBitfieldNestedArray(
// CHECK64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP1]], align 1
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 4
// CHECK64-LE-NEXT:    [[TMP4:%.*]] = and i8 [[TMP3]], -8
// CHECK64-LE-NEXT:    store i8 [[TMP4]], ptr [[TMP2]], align 4
// CHECK64-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// CHECK64-LE-NEXT:    [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2
// CHECK64-LE-NEXT:    [[TMP7:%.*]] = and i8 [[TMP6]], 31
// CHECK64-LE-NEXT:    store i8 [[TMP7]], ptr [[TMP5]], align 2
// CHECK64-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// CHECK64-LE-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 8
// CHECK64-LE-NEXT:    [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 4
// CHECK64-LE-NEXT:    [[TMP11:%.*]] = and i8 [[TMP10]], -8
// CHECK64-LE-NEXT:    store i8 [[TMP11]], ptr [[TMP9]], align 4
// CHECK64-LE-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// CHECK64-LE-NEXT:    [[TMP13:%.*]] = load i8, ptr [[TMP12]], align 2
// CHECK64-LE-NEXT:    [[TMP14:%.*]] = and i8 [[TMP13]], 31
// CHECK64-LE-NEXT:    store i8 [[TMP14]], ptr [[TMP12]], align 2
// CHECK64-LE-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP15]], align 1
// CHECK64-LE-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP16]], align 1
// CHECK64-LE-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP17]], align 2
// CHECK64-LE-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP18]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldNestedArray(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    store i8 0, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// ARM-LE-NEXT:    [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 4
// ARM-LE-NEXT:    [[TMP4:%.*]] = and i8 [[TMP3]], -8
// ARM-LE-NEXT:    store i8 [[TMP4]], ptr [[TMP2]], align 4
// ARM-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-LE-NEXT:    [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2
// ARM-LE-NEXT:    [[TMP7:%.*]] = and i8 [[TMP6]], 31
// ARM-LE-NEXT:    store i8 [[TMP7]], ptr [[TMP5]], align 2
// ARM-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-LE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-LE-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 8
// ARM-LE-NEXT:    [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 4
// ARM-LE-NEXT:    [[TMP11:%.*]] = and i8 [[TMP10]], -8
// ARM-LE-NEXT:    store i8 [[TMP11]], ptr [[TMP9]], align 4
// ARM-LE-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// ARM-LE-NEXT:    [[TMP13:%.*]] = load i8, ptr [[TMP12]], align 2
// ARM-LE-NEXT:    [[TMP14:%.*]] = and i8 [[TMP13]], 31
// ARM-LE-NEXT:    store i8 [[TMP14]], ptr [[TMP12]], align 2
// ARM-LE-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// ARM-LE-NEXT:    store i8 0, ptr [[TMP15]], align 1
// ARM-LE-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// ARM-LE-NEXT:    store i8 0, ptr [[TMP16]], align 1
// ARM-LE-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// ARM-LE-NEXT:    store i8 0, ptr [[TMP17]], align 2
// ARM-LE-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// ARM-LE-NEXT:    store i8 0, ptr [[TMP18]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldNestedArray(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    store i8 0, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// ARM-BE-NEXT:    [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 4
// ARM-BE-NEXT:    [[TMP4:%.*]] = and i8 [[TMP3]], 31
// ARM-BE-NEXT:    store i8 [[TMP4]], ptr [[TMP2]], align 4
// ARM-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-BE-NEXT:    [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2
// ARM-BE-NEXT:    [[TMP7:%.*]] = and i8 [[TMP6]], -8
// ARM-BE-NEXT:    store i8 [[TMP7]], ptr [[TMP5]], align 2
// ARM-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-BE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-BE-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 8
// ARM-BE-NEXT:    [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 4
// ARM-BE-NEXT:    [[TMP11:%.*]] = and i8 [[TMP10]], 31
// ARM-BE-NEXT:    store i8 [[TMP11]], ptr [[TMP9]], align 4
// ARM-BE-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// ARM-BE-NEXT:    [[TMP13:%.*]] = load i8, ptr [[TMP12]], align 2
// ARM-BE-NEXT:    [[TMP14:%.*]] = and i8 [[TMP13]], -8
// ARM-BE-NEXT:    store i8 [[TMP14]], ptr [[TMP12]], align 2
// ARM-BE-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// ARM-BE-NEXT:    store i8 0, ptr [[TMP15]], align 1
// ARM-BE-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// ARM-BE-NEXT:    store i8 0, ptr [[TMP16]], align 1
// ARM-BE-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// ARM-BE-NEXT:    store i8 0, ptr [[TMP17]], align 2
// ARM-BE-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// ARM-BE-NEXT:    store i8 0, ptr [[TMP18]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldNestedArray(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 4
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = and i8 [[TMP3]], 31
// AARCH64-BE-NEXT:    store i8 [[TMP4]], ptr [[TMP2]], align 4
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 2
// AARCH64-BE-NEXT:    [[TMP7:%.*]] = and i8 [[TMP6]], -8
// AARCH64-BE-NEXT:    store i8 [[TMP7]], ptr [[TMP5]], align 2
// AARCH64-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP8]], align 1
// AARCH64-BE-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 8
// AARCH64-BE-NEXT:    [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 4
// AARCH64-BE-NEXT:    [[TMP11:%.*]] = and i8 [[TMP10]], 31
// AARCH64-BE-NEXT:    store i8 [[TMP11]], ptr [[TMP9]], align 4
// AARCH64-BE-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// AARCH64-BE-NEXT:    [[TMP13:%.*]] = load i8, ptr [[TMP12]], align 2
// AARCH64-BE-NEXT:    [[TMP14:%.*]] = and i8 [[TMP13]], -8
// AARCH64-BE-NEXT:    store i8 [[TMP14]], ptr [[TMP12]], align 2
// AARCH64-BE-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP15]], align 1
// AARCH64-BE-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP16]], align 1
// AARCH64-BE-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP17]], align 2
// AARCH64-BE-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP18]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldNestedArray(struct BitfieldNestedArray *s) {
  __builtin_clear_padding(s);
}

// The raw member occupies the first byte, including padding in the fields
// member. Only padding shared by both union alternatives may be cleared.
union BitfieldUnionOverlay {
  struct BitfieldPartialEnds fields;
  unsigned char raw;
};

// CHECK64-LE-LABEL: define dso_local void @testBitfieldUnionOverlay(
// CHECK64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// CHECK64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldUnionOverlay(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldUnionOverlay(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -8
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldUnionOverlay(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -8
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldUnionOverlay(union BitfieldUnionOverlay *s) {
  __builtin_clear_padding(s);
}

enum BitfieldState { StateZero, StateOne, StateTwo, StateThree };
struct BitfieldBoolEnum {
  _Bool flag : 1;
  enum BitfieldState state : 2;
  unsigned char payload : 3;
};

// ITANIUM64-LE-LABEL: define dso_local void @testBitfieldBoolEnum(
// ITANIUM64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ITANIUM64-LE-NEXT:  [[ENTRY:.*:]]
// ITANIUM64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// ITANIUM64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ITANIUM64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// ITANIUM64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 63
// ITANIUM64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// ITANIUM64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ITANIUM64-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// ITANIUM64-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ITANIUM64-LE-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testBitfieldBoolEnum(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// WINDOWS-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// WINDOWS-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// WINDOWS-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    store i8 0, ptr [[TMP4]], align 1
// WINDOWS-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP5]], align 2
// WINDOWS-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP6]], align 1
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// WINDOWS-NEXT:    [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
// WINDOWS-NEXT:    [[TMP9:%.*]] = and i8 [[TMP8]], 3
// WINDOWS-NEXT:    store i8 [[TMP9]], ptr [[TMP7]], align 4
// WINDOWS-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// WINDOWS-NEXT:    store i8 0, ptr [[TMP10]], align 1
// WINDOWS-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// WINDOWS-NEXT:    store i8 0, ptr [[TMP11]], align 2
// WINDOWS-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// WINDOWS-NEXT:    store i8 0, ptr [[TMP12]], align 1
// WINDOWS-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP0]], i32 8
// WINDOWS-NEXT:    [[TMP14:%.*]] = load i8, ptr [[TMP13]], align 4
// WINDOWS-NEXT:    [[TMP15:%.*]] = and i8 [[TMP14]], 7
// WINDOWS-NEXT:    store i8 [[TMP15]], ptr [[TMP13]], align 4
// WINDOWS-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// WINDOWS-NEXT:    store i8 0, ptr [[TMP16]], align 1
// WINDOWS-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// WINDOWS-NEXT:    store i8 0, ptr [[TMP17]], align 2
// WINDOWS-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// WINDOWS-NEXT:    store i8 0, ptr [[TMP18]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldBoolEnum(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 63
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-LE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// ARM-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-LE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldBoolEnum(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -4
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-BE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-BE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// ARM-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-BE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldBoolEnum(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -4
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldBoolEnum(struct BitfieldBoolEnum *s) {
  __builtin_clear_padding(s);
}

// Exercise bit-precise declared types and an occupied width greater than 32.
struct BitfieldBitIntMembers {
  unsigned _BitInt(9) small : 5;
  signed _BitInt(17) medium : 13;
  unsigned _BitInt(65) wide : 61;
};

// ITANIUM64-LE-LABEL: define dso_local void @testBitfieldBitIntMembers(
// ITANIUM64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ITANIUM64-LE-NEXT:  [[ENTRY:.*:]]
// ITANIUM64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// ITANIUM64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// ITANIUM64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 127
// ITANIUM64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ITANIUM64-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ITANIUM64-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP6]], align 4
// ITANIUM64-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP7]], align 1
// ITANIUM64-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP8]], align 2
// ITANIUM64-LE-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// ITANIUM64-LE-NEXT:    store i8 0, ptr [[TMP9]], align 1
// ITANIUM64-LE-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testBitfieldBitIntMembers(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// WINDOWS-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 8
// WINDOWS-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// WINDOWS-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 8
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    store i8 0, ptr [[TMP4]], align 1
// WINDOWS-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP5]], align 2
// WINDOWS-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP6]], align 1
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// WINDOWS-NEXT:    [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 1
// WINDOWS-NEXT:    [[TMP9:%.*]] = and i8 [[TMP8]], 31
// WINDOWS-NEXT:    store i8 [[TMP9]], ptr [[TMP7]], align 1
// WINDOWS-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// WINDOWS-NEXT:    store i8 0, ptr [[TMP10]], align 2
// WINDOWS-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// WINDOWS-NEXT:    store i8 0, ptr [[TMP11]], align 1
// WINDOWS-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// WINDOWS-NEXT:    [[TMP13:%.*]] = load i8, ptr [[TMP12]], align 1
// WINDOWS-NEXT:    [[TMP14:%.*]] = and i8 [[TMP13]], 31
// WINDOWS-NEXT:    store i8 [[TMP14]], ptr [[TMP12]], align 1
// WINDOWS-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP0]], i32 16
// WINDOWS-NEXT:    store i8 0, ptr [[TMP15]], align 8
// WINDOWS-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[TMP0]], i32 17
// WINDOWS-NEXT:    store i8 0, ptr [[TMP16]], align 1
// WINDOWS-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[TMP0]], i32 18
// WINDOWS-NEXT:    store i8 0, ptr [[TMP17]], align 2
// WINDOWS-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP0]], i32 19
// WINDOWS-NEXT:    store i8 0, ptr [[TMP18]], align 1
// WINDOWS-NEXT:    [[TMP19:%.*]] = getelementptr i8, ptr [[TMP0]], i32 20
// WINDOWS-NEXT:    store i8 0, ptr [[TMP19]], align 4
// WINDOWS-NEXT:    [[TMP20:%.*]] = getelementptr i8, ptr [[TMP0]], i32 21
// WINDOWS-NEXT:    store i8 0, ptr [[TMP20]], align 1
// WINDOWS-NEXT:    [[TMP21:%.*]] = getelementptr i8, ptr [[TMP0]], i32 22
// WINDOWS-NEXT:    store i8 0, ptr [[TMP21]], align 2
// WINDOWS-NEXT:    [[TMP22:%.*]] = getelementptr i8, ptr [[TMP0]], i32 23
// WINDOWS-NEXT:    store i8 0, ptr [[TMP22]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldBitIntMembers(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 127
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// ARM-LE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ARM-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// ARM-LE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// ARM-LE-NEXT:    store i8 0, ptr [[TMP6]], align 4
// ARM-LE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// ARM-LE-NEXT:    store i8 0, ptr [[TMP7]], align 1
// ARM-LE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// ARM-LE-NEXT:    store i8 0, ptr [[TMP8]], align 2
// ARM-LE-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// ARM-LE-NEXT:    store i8 0, ptr [[TMP9]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldBitIntMembers(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -2
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// ARM-BE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// ARM-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// ARM-BE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// ARM-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// ARM-BE-NEXT:    store i8 0, ptr [[TMP6]], align 4
// ARM-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// ARM-BE-NEXT:    store i8 0, ptr [[TMP7]], align 1
// ARM-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// ARM-BE-NEXT:    store i8 0, ptr [[TMP8]], align 2
// ARM-BE-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// ARM-BE-NEXT:    store i8 0, ptr [[TMP9]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldBitIntMembers(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -2
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 10
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP4]], align 2
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 11
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP5]], align 1
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP6]], align 4
// AARCH64-BE-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 13
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP7]], align 1
// AARCH64-BE-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 14
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP8]], align 2
// AARCH64-BE-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[TMP0]], i32 15
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP9]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldBitIntMembers(struct BitfieldBitIntMembers *s) {
  __builtin_clear_padding(s);
}

// Packing permits the wide field to straddle its declared type's usual
// storage-unit boundary on Arm. Ordinary members surround the bitfield run.
struct __attribute__((packed)) BitfieldPackedMembers {
  unsigned char prefix;
  unsigned int first : 5;
  unsigned long long wide : 60;
  unsigned char suffix;
};

// ITANIUM64-LE-LABEL: define dso_local void @testBitfieldPackedMembers(
// ITANIUM64-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ITANIUM64-LE-NEXT:  [[ENTRY:.*:]]
// ITANIUM64-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// ITANIUM64-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// ITANIUM64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// ITANIUM64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// ITANIUM64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ITANIUM64-LE-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testBitfieldPackedMembers(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// WINDOWS-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 31
// WINDOWS-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP4]], align 1
// WINDOWS-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP5]], align 1
// WINDOWS-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// WINDOWS-NEXT:    store i8 0, ptr [[TMP6]], align 1
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12
// WINDOWS-NEXT:    [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 1
// WINDOWS-NEXT:    [[TMP9:%.*]] = and i8 [[TMP8]], 15
// WINDOWS-NEXT:    store i8 [[TMP9]], ptr [[TMP7]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testBitfieldPackedMembers(
// ARM-LE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testBitfieldPackedMembers(
// ARM-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -128
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testBitfieldPackedMembers(
// AARCH64-BE-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 9
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], -128
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testBitfieldPackedMembers(struct BitfieldPackedMembers *s) {
  __builtin_clear_padding(s);
}

// There are no occupied intervals: clear the entire object representation.
struct BitfieldUnnamedOnly {
  unsigned int : 3;
  unsigned int : 0;
  unsigned char : 2;
};

// LINUX-LABEL: define dso_local void @testBitfieldUnnamedOnly(
// LINUX-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// LINUX-NEXT:  [[ENTRY:.*:]]
// LINUX-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// LINUX-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// LINUX-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// LINUX-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// LINUX-NEXT:    store i8 0, ptr [[TMP1]], align 1
// LINUX-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// LINUX-NEXT:    store i8 0, ptr [[TMP2]], align 1
// LINUX-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// LINUX-NEXT:    store i8 0, ptr [[TMP3]], align 1
// LINUX-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// LINUX-NEXT:    store i8 0, ptr [[TMP4]], align 1
// LINUX-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// LINUX-NEXT:    store i8 0, ptr [[TMP5]], align 1
// LINUX-NEXT:    ret void
//
// WINDOWS-LABEL: define dso_local void @testBitfieldUnnamedOnly(
// WINDOWS-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// WINDOWS-NEXT:  [[ENTRY:.*:]]
// WINDOWS-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// WINDOWS-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// WINDOWS-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// WINDOWS-NEXT:    store i8 0, ptr [[TMP1]], align 4
// WINDOWS-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// WINDOWS-NEXT:    store i8 0, ptr [[TMP2]], align 1
// WINDOWS-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// WINDOWS-NEXT:    store i8 0, ptr [[TMP3]], align 2
// WINDOWS-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// WINDOWS-NEXT:    store i8 0, ptr [[TMP4]], align 1
// WINDOWS-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// WINDOWS-NEXT:    store i8 0, ptr [[TMP5]], align 4
// WINDOWS-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// WINDOWS-NEXT:    store i8 0, ptr [[TMP6]], align 1
// WINDOWS-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// WINDOWS-NEXT:    store i8 0, ptr [[TMP7]], align 2
// WINDOWS-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// WINDOWS-NEXT:    store i8 0, ptr [[TMP8]], align 1
// WINDOWS-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testBitfieldUnnamedOnly(
// ARM-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-NEXT:    store i8 0, ptr [[TMP1]], align 4
// ARM-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-NEXT:    store i8 0, ptr [[TMP2]], align 1
// ARM-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// ARM-NEXT:    store i8 0, ptr [[TMP3]], align 2
// ARM-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// ARM-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// ARM-NEXT:    store i8 0, ptr [[TMP5]], align 4
// ARM-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// ARM-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-NEXT:    store i8 0, ptr [[TMP7]], align 2
// ARM-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-NEXT:    store i8 0, ptr [[TMP8]], align 1
// ARM-NEXT:    ret void
//
// AARCH64-LABEL: define dso_local void @testBitfieldUnnamedOnly(
// AARCH64-SAME: ptr noundef [[S:%.*]]) #[[ATTR0]] {
// AARCH64-NEXT:  [[ENTRY:.*:]]
// AARCH64-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
// AARCH64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// AARCH64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-NEXT:    store i8 0, ptr [[TMP1]], align 4
// AARCH64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// AARCH64-NEXT:    store i8 0, ptr [[TMP2]], align 1
// AARCH64-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[TMP0]], i32 2
// AARCH64-NEXT:    store i8 0, ptr [[TMP3]], align 2
// AARCH64-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 3
// AARCH64-NEXT:    store i8 0, ptr [[TMP4]], align 1
// AARCH64-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// AARCH64-NEXT:    store i8 0, ptr [[TMP5]], align 4
// AARCH64-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// AARCH64-NEXT:    store i8 0, ptr [[TMP6]], align 1
// AARCH64-NEXT:    [[TMP7:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// AARCH64-NEXT:    store i8 0, ptr [[TMP7]], align 2
// AARCH64-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// AARCH64-NEXT:    store i8 0, ptr [[TMP8]], align 1
// AARCH64-NEXT:    ret void
//
void testBitfieldUnnamedOnly(struct BitfieldUnnamedOnly *s) {
  __builtin_clear_padding(s);
}

typedef _Bool bool6 __attribute__((ext_vector_type(6)));

// CHECK64-LABEL: define dso_local void @testPackedBooleanVectorLessThan8Elements(
// CHECK64-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// CHECK64-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// CHECK64-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// CHECK64-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 63
// CHECK64-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testPackedBooleanVectorLessThan8Elements(
// ARM-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 4
// ARM-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 63
// ARM-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-NEXT:    ret void
//
void testPackedBooleanVectorLessThan8Elements(bool6 *v) {
  __builtin_clear_padding(v);
}

typedef _Bool bool8 __attribute__((ext_vector_type(8)));

// CHECK64-LABEL: define dso_local void @testPackedBooleanVector8Elements(
// CHECK64-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// CHECK64-NEXT:  [[ENTRY:.*:]]
// CHECK64-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
// CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// CHECK64-NEXT:    ret void
//
// ARM-LABEL: define dso_local void @testPackedBooleanVector8Elements(
// ARM-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// ARM-NEXT:  [[ENTRY:.*:]]
// ARM-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
// ARM-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
// ARM-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 4
// ARM-NEXT:    ret void
//
void testPackedBooleanVector8Elements(bool8 *v) {
  __builtin_clear_padding(v);
}

typedef _Bool bool12 __attribute__((ext_vector_type(12)));

// CHECK64-LE-LABEL: define dso_local void @testPackedBooleanVectorMoreThan8Elements(
// CHECK64-LE-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testPackedBooleanVectorMoreThan8Elements(
// ARM-LE-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 1
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testPackedBooleanVectorMoreThan8Elements(
// ARM-BE-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testPackedBooleanVectorMoreThan8Elements(
// AARCH64-BE-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 2
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 15
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 2
// AARCH64-BE-NEXT:    ret void
//
void testPackedBooleanVectorMoreThan8Elements(bool12 *v) {
  __builtin_clear_padding(v);
}

typedef _Bool bool33 __attribute__((ext_vector_type(33)));

// CHECK64-LE-LABEL: define dso_local void @testPackedBooleanVectorWithFullyPaddingBytes(
// CHECK64-LE-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// CHECK64-LE-NEXT:  [[ENTRY:.*:]]
// CHECK64-LE-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
// CHECK64-LE-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// CHECK64-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// CHECK64-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// CHECK64-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// CHECK64-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// CHECK64-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// CHECK64-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// CHECK64-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// CHECK64-LE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// CHECK64-LE-NEXT:    ret void
//
// ARM-LE-LABEL: define dso_local void @testPackedBooleanVectorWithFullyPaddingBytes(
// ARM-LE-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// ARM-LE-NEXT:  [[ENTRY:.*:]]
// ARM-LE-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
// ARM-LE-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 4
// ARM-LE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 4
// ARM-LE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// ARM-LE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 4
// ARM-LE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// ARM-LE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-LE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-LE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// ARM-LE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-LE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-LE-NEXT:    ret void
//
// ARM-BE-LABEL: define dso_local void @testPackedBooleanVectorWithFullyPaddingBytes(
// ARM-BE-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// ARM-BE-NEXT:  [[ENTRY:.*:]]
// ARM-BE-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
// ARM-BE-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 4
// ARM-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// ARM-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 8
// ARM-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// ARM-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 8
// ARM-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// ARM-BE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// ARM-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// ARM-BE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// ARM-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// ARM-BE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// ARM-BE-NEXT:    ret void
//
// AARCH64-BE-LABEL: define dso_local void @testPackedBooleanVectorWithFullyPaddingBytes(
// AARCH64-BE-SAME: ptr noundef [[V:%.*]]) #[[ATTR0]] {
// AARCH64-BE-NEXT:  [[ENTRY:.*:]]
// AARCH64-BE-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
// AARCH64-BE-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// AARCH64-BE-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 0
// AARCH64-BE-NEXT:    [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 8
// AARCH64-BE-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], 1
// AARCH64-BE-NEXT:    store i8 [[TMP3]], ptr [[TMP1]], align 8
// AARCH64-BE-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[TMP0]], i32 5
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP4]], align 1
// AARCH64-BE-NEXT:    [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0]], i32 6
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP5]], align 2
// AARCH64-BE-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[TMP0]], i32 7
// AARCH64-BE-NEXT:    store i8 0, ptr [[TMP6]], align 1
// AARCH64-BE-NEXT:    ret void
//
void testPackedBooleanVectorWithFullyPaddingBytes(bool33 *v) {
  __builtin_clear_padding(v);
}